User Guide

8965 N/B Maintenance
8965 N/B Maintenance
73
SMB / I2C Interface
I/O pads for SPCLK[2:1] / SPDAT[2:1] above are powered by VCC33GFX (i.e., 3.3V I/O).
All other pins in the above table are powered by VCC15AGP (i.e., 1.5V I/O)
Signal Name AGP Name Pin # I/O Signal Description
SBPLCLK
GIRDY AL5 IO
I2C Serial Bus Clock for Panel (Muxed on AGP
Bus Pins).
SBPLDAT
GC#BE1 AL3 IO
I2C Serial Bus Data for Panel (Muxed on AGP
Bus Pins).
SBDDCCLK
GREQ AD4 IO
I2C Serial Bus Clock for CRT DDC (Muxed on
AGP Bus Pins).
SBDDCDAT
GGNT AD5 IO
I2C Serial Bus Data for CRT DDC (Muxed on
AGP Bus Pins).
SPCLK2
SPCLK1 /
CAPD12
SPDAT2,
SPDAT1 /
CAPD13
n/a
n/a
n/a
n/a
T3
V3
T4
V4
IO Serial Port (SMB/I2C) Clock and Data. The
SPCLKn pins are the clocks for serial data
transfer. The SPDATn pins are the data signals
used for serial data transfer. SPxxx1 is typically
used for DVI monitor communications and
SPxxx2 is typically used for DDC for CRT
monitor communications. These pins are
programmed via “Sequencer” graphics
registers (port 3C5) in the “Extended” VGA
register space (see the UniChrome-II Graphics
Registers document for additional details). The
SPxxx1 registers are programmed via 3C5.31
(“IIC Serial Port Control 1”) and the SPxxx2
registers are programmed via 3C5.26 (“IIC Serial
Port Control 0”). In both registers, the clock out
state is programmed via bit-5 and the data out state
via bit-4, clock in status may be read in bit-3 and
data in status in bit-2, and the port may be enabled
via bit-0.
Dedicated Digital Video Port 0 (DVP0)
The above pins may be connected to an external TV Encoder chip such as a VIA VT1622A or
VT1622AM for driving a TV set.
I/O pads for the pins on this page are powered by VCC33GFX (3.3V I/O).
Signal Name Pin # I/O Signal Description
TVD11 / DVP0D11 /
CAPD11,
TVD10 / DVP0D10 / CAPD10
/ strap,
TVD9 / DVP0D9 / CAPD9 /
strap,
TVD8 / DVP0D8 / CAPD8 /
strap,
TVD7 / DVP0D7 / CAPD7 /
strap,
TVD6 / DVP0D6 / CAPD6 /
strap,
TVD5 / DVP0D5 / CAPD5 /
strap,
TVD4 / DVP0D4 / CAPD4 /
strap,
TVD3 / DVP0D3 / CAPD3 /
strap,
TVD2 / DVP0D2 / CAPD2 /
strap,
TVD1 / DVP0D1 / CAPD1 /
strap,
TVD0 / DVP0D0 / CAPD0 /
strap
AA6
AB6
AB5
Y7
Y6
Y5
AA4
Y2
Y3
AA5
W2
W1
O
TV Encoder 0 Data.
To configure DVP0 as a TV Out interface port,
pins DVP0D[6:5] must be strapped high.
Note: One TV Encoder interface is supported
through either DVP0 or GDVP1.
TVHS / DVP0HS / CAPHS W4 O TV Encoder 0 Horizontal Sync. Internally pulled
down.
TVVS / DVP0VS / CAPVS V1 O TV Encoder 0 Vertical Sync. Internally pulled
down.
TVDE / DVP0DE W3 O TV Encoder 0 Display Enable. Internally pulled
down.
TVCLKIN / DVP0DET /
CAPBCLK
V2 I TV Encoder 0 Clock In. Feedback from TV
encoder. Internally pulled down.
TVCLK / DVP0CLK /
CAPACLK
Y4 O TV Encoder 0 Clock Out. Output to TV encoder.
Internally pulled down.
5.2 PN800 North Bridge - 6
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