User Guide

8965 N/B Maintenance
8965 N/B Maintenance
72
Ultra V-Link Interface
Signal Name Pin # I/O Signal Description
VD15,
VD14,
VD13,
VD12,
VD11,
VD10,
VD9,
VD8,
VD7,
VD6,
VD5,
VD4,
VD3,
VD2,
VD1,
VD0
AP13
AN13
AR6
AT6
AM12
AP12
AN6
AM7
AP11
AM11
AP7
AR7
AR11
AN10
AR8
AP8
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
V-Link Data Bus. During system initialization, VD[7:0] are
used to transmit strap information from the South Bridge (the
straps are not on the VD pins but are on the indicated pins of the
South Bridge chip). Check the strap pin table for details.
VPAR
AT7 IO
V-Link Parity.
VBE#
AN7 IO
V-Link Byte Enable.
UPCMD
AN12 I
V-Link Command from Client (South Bridge) to Host
(North Bridge).
UPSTB+
AM10 I
V-Link Strobe from Client to Host.
UPSTB–
AM9 I
V-Link Complement Strobe from Client to Host.
DNCMD
AP10 O
V-Link Command from Host (North Bridge) to Client
(South Bridge).
DNSTB+
AN9 O
V-Link Strobe from Host to Client.
DNSTB–
AP9 O
V-Link Complement Strobe from Host to Client.
Note: I/O pads for the pins in the above table are powered by VCC15VL. Input voltage levels
are referenced to VLVREF.
CRT Interface
Signal Name Pin # I/O Signal Description
AR
R1 AO Analog Red. Analog red output to the CRT monitor.
AG
R2 AO Analog Green. Analog green output to the CRT monitor.
AB
R3 AO Analog Blue. Analog blue output to the CRT monitor.
HSYNC
U4 O Horizontal Sync. Output to CRT.
VSYNC
U3 O Vertical Sync. Output to CRT.
RSET
V7 AI Reference Resistor. Tie to GNDDAC through an external 82 Ω
1%%resistor to control the RAMDAC full-scale current value.
See Design Guide for details.
I/O pads for the pins in the above table are powered by VCC33GFX (i.e., 3.3V I/O).
Digital Power / Ground
Signal Name Pin # I/O Signal Description
VTT
(see pin list
s
P Power for CPU I/O Interface Logic (15 Pins).
Typical 1.65V (CPU dependent)
VCC25MEM
(see pin list
s
P Power for Memory I/O Interface Logic (25
Pins). 2.5V ±5%.
VCC15VL
AD16-17 P Power for V-Link I/O Interface Logic (2 Pins).
1.5V ±5%
VCC15AGP
(see pin list
s
P Power for AGP Bus I/O Interface Logic (6
Pins). 1.5V ±5%
VCC33GFX
V13, W13,
Y13
P
Power for Graphics Display I/O Logic (3 Pins).
3.3V ±5%
VCC15
(see pin list
s
P Power for Internal Logic (51 Pins). 1.5V ±5%
VSUS15
AT14 P Suspend Power (1 Pin). 1.5V ±5%
GND
(see pin list
s
P Digital Ground (161 Pins). Connect to main
ground plane.
5.2 PN800 North Bridge - 5
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