User Guide

8965 N/B Maintenance
8965 N/B Maintenance
71
AGP 8x / 4x Bus Interface (Continued)
Signal Name Pin # I/O Signal Description
GSBA[7:0]#
(GSBA[7:0] for
4x)
AE1,
AE4,
AE3,
AE2,
AD2,
AC3,
AC4,
AC1
I Side Band Address. Provides an additional bus to pass address
and command information from the master (graphics controller)
to the target (North Bridge).
These pins are ignored until enabled.
GSBSTBF
(GSBSTB for
4x), GSBSTBS
(GSBSTB# for
4x)
AD3
AD1
I Side Band Strobe. Driven by the master to provide timing for
GSBA[7:0]. 8x mode uses GSBSTBF (“First” strobe) and
GSBSTBS (“Second” strobe). These signals are interpreted as
GSBSTB & GSBSTB# for AGP4x.
GST[2:0]
AE6,
AE5,
AD6
O Status (AGP only). Provides information from the arbiter to a
master to indicate what it may do. Only valid while GGNT# is
asserted.
000 Indicates that previously requested low priority read or
flush data
is being returned to the master (graphics controller).
001 Indicates that previously requested high priority read data is
being
returned to the master.
010 Indicates that the master is to provide low priority write
data for a
previously enqueued write command.
011 Indicates that the master is to provide high priority write
data for a
previously enqueued write command.
100 Reserved. (arbiter must not issue, may be defined in the
future).
101 Reserved. (arbiter must not issue, may be defined in the
future).
110 Reserved. (arbiter must not issue, may be defined in the
future).
111 Indicates that the master (graphics controller) has been
given
permission to start a bus transaction. The master may enqueue
AGP requests by asserting GPIPE# or start a PCI transaction by
asserting GFRAME#. GST[2:0] are always outputs from the
target (North Bridge) and inputs to the master (graphics
controller).
AGP 8x / 4x Bus Interface (Continued)
Signal Name Pin # I/O Signal Description
GWBF (GWBF#
for 4x)
AB2 I
Write Buffer Full.
GRBF (GRBF#
for 4x)
AE7 I Read Buffer Full. Indicates if the master (graphics controller)
is ready to accept previously requested low priority read data.
When GRBF# is asserted,
the North Bridge will not return low priority read data to the
graphics controller.
GREQ (GREQ#
for 4x)
AD4 I Request. Master (graphics controller) request for use of the
AGP bus.
GGNT (GGNT#
for 4x)
AD5 O Grant. Permission is given to the master (graphics controller) to
use the AGP bus.
GSERR
(GSERR# for 4x)
AN1 IO
System Error.
GSTOP
(GSTOP# for 4x)
AM3 IO Stop. Asserted by the target to request the master to stop the
current transaction. Interpreted as active high for AGP 8x.
Note: I/O pads for all pins on this page are powered by VCC15AGP. Input voltage levels are
referenced to AGPVREF.
Note: The AGP interface pins can be optionally configured as additional interfaces for
connecting to external display devices. For simplification of the AGP pin description tables
above and on the next page, that multiplexing is not shown here (see “Additional I2C
Interfaces” and “Digital Display” pin description tables later in this document for more
information).
Note: I/O pads for all pins on this page are powered by VCC15AGP. Input voltage levels are
referenced to AGPVREF.
Note: The AGP interface pins can be optionally configured as additional interfaces for
connecting to external display devices. For simplification of the AGP pin description tables
above and on the next page, that multiplexing is not shown here (see “Additional I2C
Interfaces” and “Digital Display” pin description tables later in this document for more
information).
Note: Separate system interrupts are not provided for AGP. The AGP connector provides
interrupts via PCI bus INTA-B#.
Note: A separate reset is not required for the AGP bus (RESET# resets both PCI and AGP buses)
Note: Two mechanisms are provided by the AGP bus to enqueue master requests: GPIPE#
(to send addresses multiplexed on the AD lines) and the GSBA port (to send addresses
unmultiplexed). AGP masters implement one or the other or select one at initialization time
(they are not allowed to change during runtime). Only one of the two will be used; the signals
associated with the other will not be used. GRBF# has an internal pullup to maintain it in the
de-asserted state in case it is not implemented on the master device. AGP 8x mode allows only
GSBA (GPIPE# isn’t used in 8x mode).
Note: AGP 8x signal levels are 0V and 0.8V. AGP 8x mode maintains most signals at a low level
when inactive resulting in no current flow.
5.2 PN800 North Bridge - 4
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