User Guide

8965 N/B Maintenance
8965 N/B Maintenance
69
DDR SDRAM Interface – “A” Data
Signal Name Pin # I/O Signal Description
MDA[63:0]
(see pin
lists)
IO Memory Data. These signals are connected to the DRAM data
bus.
Output drive strength may be set by Device 0 Function 3 RxE2.
DQMA[7:0]
AT16,
AP20,
AP24,
AN32,
AD35,
V34, L33,
D36
O Data Mask. Data mask of each byte lane. Output drive strength
may be set by Device 0 Function 3 RxE2.
DQSA[7:0]# AR16,
AN20,
AT24,
AT33,
AD34,
U34, L31,
D35
IO DDR Data Strobe. Data strobe of each byte lane. Output drive
strength may be set by Device 0 Function 3 RxE0.
CSA[3:0]#
AP25,
AP29,
AR25,
AT25
O Chip Select. Chip select of each bank. Output drive strength
may be set by Device 0 Function 3 RxE4.
CKEA[3:0]
L34, R35,
M35, T33
O Clock Enables. Clock enables for each DRAM bank for
powering down the SDRAM or clock control for reducing
power usage and for reducing heat / temperature in high-speed
memory systems.
DDR SDRAM Interface – “B” Data
Signal Name Pin # I/O Signal Description
MDB[63:0]
(see pin
lists)
IO Memory Data. These signals are connected to the DRAM data
bus.
Output drive strength may be set by Device 0 Function 3 RxE2.
DQMB[7:0]
AN18,
AP22,
AR28,
AG32,
Y33,
N35,
H36, A34
O Data Mask. Data mask of each byte lane. Output drive strength
may be set by Device 0 Function 3 RxE2.
DQSB[7:0]# AP18,
AR22,
AT28,
AG33,
Y34,
N34,
H34, A33
IO DDR Data Strobe. Data strobe of each byte lane. Output drive
strength may be set by Device 0 Function 3 RxE0.
CSB[3:0]#
AP28,
AR29,
AT29,
AT30
O Chip Select. Chip select of each bank. Output drive strength
may be set by Device 0 Function 3 RxE4.
CKEB[3:0]
J35, K31,
J33, K32
O Clock Enables. Clock enables for each DRAM bank for
powering down the SDRAM or clock control for reducing
power usage and for reducing heat / temperature in high-speed
memory systems.
5.2 PN800 North Bridge - 2
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