User Guide

8965 N/B Maintenance
8965 N/B Maintenance
68
CPU Interface
Signal Name Pin # I/O Signal Description
HA[35:3]#
(see pin
lists)
IO Host CPU Address Bus. Connect to the address bus of the host
CPU. Inputs during CPU cycles and driven by the North Bridge
during cache snooping operations.
Address signals up through HA[35]# allow future support of a
64 Gbyte memory space (the current design supports up to
HA[33]# for support of 16 GB)..
HADSTB [1:0]#
C26, A22 IO Host CPU Address Strobe. Source synchronous strobes used
to transfer HA[31:3]# and HREQ[4:0]# at a 2x transfer rate.
HASTB1# is the strobe for HA[31:17]# and HASTB0# is the
strobe for HA[16:3] and HREQ[4:0]#.
HD[63:0]#
(see pin
lists)
IO Host CPU Data. These signals are connected to the CPU data
bus.
HDBI[3:0]#
A5, J3,
B13, A6
IO Host CPU Dynamic Bus Inversion. Driven along with
HD[63:0]# to indicate if the associated signals are inverted or
not. Used to limit the number of simultaneously switching
signals to 8 for the associated 16-bit data pin group (HDBI3#
for
HD[63:48]#, HDBI2# for HD[47:32]#, HDBI1# for
HD[31:16]#, and HDBI0# for HD[15:0]#). HDBIn# is asserted
such that the number of data bits driven low for the
corresponding group does not exceed 8.
HDSTBP [3:0]#
HDSTBN [3:0]#
D1, H3,
E13, F8
E1, H2,
D13, D8
IO Host CPU Differential Data Strobes. Source synchronous
strobes used to transfer HD[63:0]# and HDBI[3:0]# at a 4x
transfer rate. HDSTBP3# / HDSTBN3# are the strobes for
HD[63:48]# & HDBI3#; HDSTBP2# / HDSTBN2# are the
strobes for HD[47:32]# & HDBI2#; HDSTBP1# / HDSTBN1#
are the strobes for HD[31:16]# & HDBI1#; and HDSTBP0# /
HDSTBN0# are the strobes for HD[15:0]# & HDBI0#.
ADS#
A19 IO Address Strobe. The CPU asserts ADS# in T1 of the CPU bus
cycle.
DBSY#
B19 IO Data Bus Busy. Used by the data bus owner to hold the data
bus for transfers requiring more than one cycle.
DRDY#
C19 IO Data Ready. Asserted for each cycle that data is transferred.
HIT#
C17 IO Hit. Indicates that a caching agent holds an unmodified version
of the requested line.
Also driven in conjunction with HITM# by the target to extend
the snoop window.
HITM#
F16 I Hit Modified. Asserted by the CPU to indicate that the address
is modified in the L1 cache and needs to be written back.
CPU Interface (Continued)
Signal Name Pin # I/O Signal Description
HLOCK#
F18 I Host Lock. All CPU cycles sampled with the assertion of
HLOCK# and ADS# until the negation of HLOCK# must be
atomic.
HREQ[4:0]#
F19, E19,
D20, C20,
D19
IO Request Command. Asserted during both clocks of the request
phase. In the first clock, the signals define the transaction type
to a level of detail that is sufficient to begin a snoop request. In
the second clock, the signals carry additional information
to define the complete transaction type.
HTRDY#
G18 IO Host Target Ready. Indicates that the target of the processor
transaction is able to enter the data transfer phase.
RS[2:0]#
B17, D18,
B18
IO Response Signals. Indicates the type of response per the table
below:
RS[2:0]# Response type RS[2:0]# Response type
000 Idle State 100 Hard Failure
001 Retry Response 101 Normal Without Data
010 Defer Response 110 Implicit Writeback
011 Reserved 111 Normal With Data
DPWR#
G15 O Data Bus Power Reduction. Request to reduce power on the
mobile CPU data bus input buffer. Connect to mobile CPU if
used.
BREQ0#
E18 O Bus Request 0. Bus request output to CPU.
BPRI#
C16 IO Priority Agent Bus Request. The owner of this signal will
always be the next bus owner. This signal has priority over
symmetric bus requests and causes the current symmetric owner
to stop issuing new transactions unless the HLOCK# signal is
asserted. The PN800 drives this signal to gain control of the
processor bus.
BNR#
C18 IO Block Next Request. Used to block the current request bus
owner from issuing new requests. This signal is used to
dynamically control the processor bus pipeline depth.
DEFER#
E17 IO Defer. The PN800 uses a dynamic deferring policy to optimize
system performance. The PN800 also uses the DEFER# signal
to indicate a processor retry response.
CPURST#
K6 O CPU Reset. Reset output to CPU. External pullup and filter
capacitor to ground should be provided per CPU manufacturer’s
recommendations.
Note: Clocking of the CPU interface is performed with HCLK+ and HCLK– (see clock pin
description group).
5.2 PN800 North Bridge - 1
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