User Guide

8965 N/B Maintenance
8965 N/B Maintenance
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 DQS edge-aligned with data for READs; center-aligned with data for WRITEs
 Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
 Bidirectional data strobe (DQS) transmitted/received with data—i.e.,source-synchronous data capture
 Differential clock inputs (CK and CK# can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.)
 Four internal device banks for concurrent operation
 Selectable burst lengths: 2, 4 or 8
 Auto precharge option
 Auto Refresh and Self Refresh Modes
 15.6µs (MT4VDDT864H, MT8VDDT1664HD), 7.8125µs (MT4VDDT1664H, MT8VDDT3264HD,
MT8VDDT6464HD) maximum average periodic refresh interval
 Serial Presence Detect (SPD) with EEPROM
 Fast data transfer rates PC2100 or PC1600
 Selectable READ CAS latency for maximum compatibility
 Gold-plated edge contacts
1.2.8 PHY: 3.3-V 10Base-T/100Base-TX Integrated PHY Receiver is a
Low-power, Physical-layer Device (PHY)
The VT6103L is a Physical Layer device for Ethernet 10Base-T and 100Base-TX using category 5 Unshielded and
Type 1 Shielded cables. This VLSI device is designed for easy implementation of 10 / 100 Mb/s Fast Ethernet LANs.
It interfaces to a MAC through an MII interface ensuring interoperability between products from different vendors.
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