User Guide

8965 N/B Maintenance

 Firmware Hub Hardware Interface Mode

- 5-signal communication interface supporting byte Read and Write

- 33 MHz clock frequency operation

- WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block

- Block Locking Register for all blocks

- Standard SDP Command Set

- Data# Polling and Toggle Bit for End-of-Write detection

- 5 GPI pins for system design flexibility

- 4 ID pins for multi-chip selection

1.2.7 Memory System

1.2.7.1 64MB, 128MB, 256MB, 512MB (x64) 200-Pin DDR SDRAM SODIMMs

 JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)

 Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components

 64MB (8 Meg x 64 [H]); 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB (64 Meg

x 64 [HD])

 VDD= VDDQ= +2.5V ±0.2V

 VDDSPD = +2.2V to +5.5V

 2.5V I/O (SSTL_2 compatible)

 Commands entered on each positive CK edge

MiTac Secret

Confidential Document