User Guide

8965 N/B Maintenance

pixel / clock) or DDR (2 pixels / clock) modes. UXGA and higher resolutions require dual-edge data transfer (DDR)

mode which is supported by the VIA VT1631 LVDS transmitter chip Digital Video Port 0 (DVP0) is normally used

for interfacing to a TV encoder (such as the VIA VT1622A or VT1622AM using 3.3V signal levels), however if

DVP0 is used for video capture, Digital Video Port 1 (GDVP1) may be configured for support of an external TV

encoder (VIA VT1623 or VT1623M using low-voltage 1.5V signal levels). If GDVP1 is not being used for TV out, it

can optionally be used to drive a DVI monitor via an external TMDS transmitter chip (such as the VIA VT1632) The

flexible display configurations of the PN800 allow support of a flat panel (LVDS interface) or flat panel monitor

(TMDS / DVI interface), TV display and CRT display at the same time. Internally the PN800 North Bridge provides

two separate display engines, so if two display devices are connected, each can display completely different

information at different resolutions, pixel depths and refresh rates. If more than two display devices are connected, the

additional displays must have the same resolution, pixel depth and refresh rate as one of the first two. The maximum

display resolutions supported for one display device are listed in the table below. If more than one display is

implemented (i.e., if both display engines are functioning at the same time), then available memory bandwidth may

limit the display resolutions supported on one or both displays. This will be dependent on many factors including

primarily clock rates and memory speeds (contact VIA for additional information).

1.2.4 VT8235CE Highly Integrated South Bridge

The VT8235 Version CE South Bridge is a high integration, high performance, power-efficient and high compatibility

device that supports Intel and non-Intel based processor to V-Link bus bridge functionality to make a complete

Microsoft PC2001-compliant PCI/LPC system. The VT8235 Version CE includes standard intelligent peripheral

controllers.

a) IEEE 802.3 compliant 10 / 100 Mbps PCI bus master Ethernet MAC with standard MII interface to external

PHY ceiver.

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