User Guide

8965 N/B Maintenance
8965 N/B Maintenance
10
AGP Interface
The PN800 AGP controller is AGP 3.0 compliant with up to 2.1 GB / second data transfer rate capability. It
supports asynchronous AGP and CPU interfaces for flexible system configuration. Deep read (1024 byte) and write
(512 byte) FIFOs are integrated for optimal bus utilization and minimum data transfer latency.
Memory Controller
The PN800 SDRAM Controller supports two sets of 64-bit memory data, address and control signals to minimize
signal loading and up to 4 double-sided DDR400 / 333 / 266 DIMMs for 8 GB maximum physical memory. The
DDR DRAM interface allows zero wait-state data transfer bursting between the DRAM and the memory
controller’s data buffers. The different banks of DRAM can be composed of an arbitrary mixture of 64 / 128 / 256 /
512 / 1024Mb DRAMs in x8 and x16 configurations. The DRAM controller can run either synchronous or pseudo-
synchronous with the host CPU bus. The PN800 North Bridge is pin compatible with the PN880 North Bridge
which connects to the memory modules in exactly the same manner while supporting true 128-bit operation
(simultaneous memory access on both sets of 64-bit memory data / address / control signals).
Ultra V-Link
The PN800 North Bridge interfaces to the South Bridge through a high speed (up to 1 GB/sec) 8x, 66 MHz Data
Transfer interconnect bus called “Ultra V-Link”. Deep pre-fetch and post-write buffers are included to allow for
concurrent CPU and Vlink operation. The combined PN800 North Bridge and VT8235-CE South Bridge system
supports enhanced PCI bus commands such as “Memory-Read-Line”, “Memory-Read-Multiple” and “Memory-
Write-Invalid” commands to minimize snoop overhead. In addition, advanced features are supported such as CPU
write-back forward to PCI master, and CPU write-back merged with PCI post write buffers to minimize PCI master
read latency and DRAM utilization. Delay transaction and read caching mechanisms are also implemented for
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