Service manual

8224 N/B Maintenance
8224 N/B Maintenance
86
5.1 Intel 945G/945P North Bridge (3)
DDR2 DRAM Channel A Interface
Signal Name Type Description
SCLK_A[5:0] O
SSTL-1.8
SDRAM Differential Clock:
(3 per DIMM). SCLK_Ax and its complement SCLK_Ax# signal
make a differential clock pair output. The crossing of the positive
edge of SCLK_Ax and the negative edge of its complement
SCLK_Ax# are used to sample the command and control signals on
the SDRAM.
SCLK_A[5:0]# O
SSTL-1.8
SDRAM Complementary Differential Clock:
(3 per DIMM). These are the complementary Differential DDR2
Clock signals.
SCS_A[3:0]# O
SSTL-1.8
Chip Select:
(1 per Rank). These signals select particular SDRAM components
during the active state. There is one chip select for each SDRAM
rank.
SMA_A[13:0] O
SSTL-1.8
Memory Address:
These signals are used to provide the multiplexed row and column
address to the SDRAM.
SBS_A[2:0] O
SSTL-1.8
Bank Select:
These signals define which banks are selected within each SDRAM
rank.
DDR2: 1-Gb technology is 8 banks.
SRAS_A# O
SSTL-1.8
Row Address Strobe:
This signal is used with SCAS_A# and SWE_A# (along with
SCS_A#) to define the SDRAM commands.
SCAS_A# O
SSTL-1.8
Column Address Strobe:
This signal is used with SRAS_A# and SWE_A# (along with
SCS_A#) to define the SDRAM commands.
SWE_A# O
SSTL-1.8
Write Enable:
This signal is used with SCAS_A# and SRAS_A# (along with
SCS_A#) to define the SDRAM commands.
SDQ_A[63:0] I/O
SSTL-1.8
2X
Data Lines:
The SDQ_A[63:0] signals interface to the SDRAM data bus.
SDM_A[7:0] O
SSTL-1.8
2X
Data Mask:
When activated during writes, the corresponding data groups in
the SDRAM are masked. There is one SDM_Ax bit for every data
byte lane.
SDQS_A[7:0] I/O
SSTL-1.8
2X
Data Strobes:
For DDR2, SDQS_Ax and its complement SDQS_Ax# signal
make up a differential strobe pair. The data is captured at the crossing
point of SDQS_Ax and its complement SDQS_Ax# during read and
write transactions.
DDR2 DRAM Channel B Interface
Signal Name Type Description
SCLK_B[5:0] O
SSTL-1.8
SDRAM Differential Clock:
(3 per DIMM). SCLK_Bx and its complement SCLK_Bx# signal
make a differential clock pair output. The crossing of the positive
edge of SCLK_Bx and the negative edge of its complement
SCLK_Bx# are used to sample the command and control signals on
the SDRAM.
SCLK_B[5:0]# O
SSTL-1.8
SDRAM Complementary Differential Clock:
(3 per DIMM). These are the complementary Differential DDR2
Clock signals.
SCS_B[3:0]# O
SSTL-1.8
Chip Select:
(1 per Rank). These signals select particular SDRAM components
during the active state. There is one chip select for each SDRAM
rank.
SMA_B[13:0] O
SSTL-1.8
Memory Address:
These signals are used to provide the multiplexed row and column
address to the SDRAM.
SBS_B[2:0] O
SSTL-1.8
Bank Select:
These signals define which banks are selected within each SDRAM
rank.
DDR2: 1-Gb technology is 8 banks.
SRAS_B# O
SSTL-1.8
Row Address Strobe:
This signal is used with SCAS_B# and SWE_B# (along with
SCS_B#) to define the SDRAM commands.
DDR2 DRAM Channel A Interface (Continued)
Signal Name Type Description
SDQS_A[7:0]# I/O
SSTL-1.8
2X
Data Strobe Complements:
These are the complementary DDR2 strobe signals.
SCKE_A[3:0] O
SSTL-1.8
Clock Enable:
(1 per Rank). SCKE_Ax is used to initialize the SDRAMs during
power-up, to power-down SDRAM ranks, and to place all SDRAM
ranks into and out of self-refresh during Suspend-to-RAM.
SODT_A[3:0] O
SSTL-1.8
On Die Termination:
Active On-die Termination Control signals for DDR2 devices.
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