Service manual

8224 N/B Maintenance
8224 N/B Maintenance
85
5.1 Intel 945G/945P North Bridge (2)
Host Interface Signals (Continued)
Signal Name Type Description
HDSTBP[3:0]#
HDSTBN[3:0]#
I/O
GTL+
Differential Host Data Strobes:
These signals are the differential source synchronous strobes used to
transfer HD[63:0]# and HDINV[3:0]# at 4x transfer rate.
These signals are named this way because they are not level sensitive.
Data is captured on the falling edge of both strobes. Hence they are
pseudo-differential, and not true differential.
Strobe Data Bits
HDSTBP3#, HDSTBN3# HD[63:48] HDINV3#
HDSTBP2#, HDSTBN2# HD[47:32] HDINV2#
HDSTBP1#, HDSTBN1# HD[31:16] HDINV1#
HDSTBP0#, HDSTBN0# HD[15:00] HDINV0#
HHITM# I/O
GTL+
Hit Modified:
This signal indicates that a caching agent holds a modified version of
the requested line and that this agent assumes responsibility for
providing the line. In addition, HHITM# is driven in conjunction with
HHIT# to extend the snoop window.
HLOCK# I/O
GTL+
Host Lock:
All processor bus cycles sampled with the assertion of HLOCK#
and HADS#, until the negation of HLOCK# must be atomic (i.e., no
DMI or PCI Express accesses to DRAM are allowed when HLOCK#
is asserted by the processor).
HPCREQ# I
GTL+
2X
Precharge Request:
The processor provides a “hint” to the (G)MCH that it is OK to close
the DRAM page of the memory read request with which the hint is
associated. The (G)MCH uses this information to schedule the read
request to memory using the special “AutoPrecharge” attribute. This
causes the DRAM to immediately close (Precharge) the page after the
read data has been returned. This allows subsequent processor
requests to more quickly access information on other DRAM pages,
since it will no longer be necessary to close an open page prior to
opening the proper page.
HPCREQ# is asserted by the requesting agent during both halves of
Request Phase. The same information is provided in both halves of
the request phase.
HREQ[4:0]# I/O
GTL+
2X
Host Request Command:
These signals define the attributes of the request. HREQ[4:0]# are
transferred at 2x rate. They are asserted by the requesting agent
during both halves of Request Phase. In the first half, the
signals define the transaction type to a level of detail that is sufficient
to begin a snoop request. In the second half, the signals carry
additional information to define the complete transaction type.
Host Interface Signals (Continued)
Signal Name Type Description
HTRDY# O
GTL+
Host Target Ready:
This signal indicates that the target of the processor transaction is able
to enter the data transfer phase.
HRS[2:0]# O
GTL+
Host Response Status:
These signals indicate the type of response as shown below:
000 = Idle state
001 = Retry response
010 = Deferred response
011 = Reserved (not driven by (G)MCH)
100 = Hard Failure (not driven by (G)MCH)
101 = No data response
110 = Implicit Write back
111 = Normal data response
BSEL[2:0] I
COMS
Bus Speed Select:
At the de-assertion of RSTIN#, the value sampled on these pins
determines the expected frequency of the bus.
HRCOMP I/O
COMS
Host RCOMP:
This signal is used to calibrate the Host GTL+ I/O buffers.
This signal is powered by the Host Interface termination rail (V
TT
).
HSCOMP I/O
COMS
Slew Rate Compensation:
This is the compensation signal for the Host Interface.
HSWING I
A
Host Voltage Swing:
This signal provides the reference voltage used by FSB RCOMP
circuits. HSWING is used for the signals handled by HRCOMP.
HDVREF I
A
Host Reference Voltage:
Voltage input for the data, address, and common clock signals of the
Host GTL interface.
HACCVREF I
A
Host Reference Voltage:
Reference voltage input for the Address, and Common clock signals
of the Host GTL interface.
Note:
Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination
voltage of the Host Bus (VTT).
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