Service manual
8224 N/B Maintenance
8224 N/B Maintenance
84
5. Pin Descriptions of Major Components
5.1 Intel 945G/945P North Bridge (1)
Host Interface Signals
Signal Name Type Description
HADS#
I/O
GTL+
Address Strobe:
The processor bus owner asserts HADS# to indicate the first of two
cycles of a request phase. The (G)MCH can assert this signal for
snoop cycles and interrupt messages.
HBNR# I/O
GTL+
Block Next Request:
HBNR# is used to block the current request bus owner from issuing
new requests. This signal is used to dynamically control the processor
bus pipeline depth.
HBPRI#
O
GTL+
Priority Agent Bus Request:
The (G)MCH is the only Priority Agent on the processor bus. It
asserts this signal to obtain the ownership of the address bus. This
signal has priority over symmetric bus requests and will cause the
current symmetric owner to stop issuing new transactions unless the
HLOCK# signal was asserted.
HBREQ0#
I/O
GTL+
Bus Request 0:
The (G)MCH pulls the processor’s bus HBREQ0# signal low during
HCPURST#. The processor samples this signal on the
active-toinactive transition of HCPURST#. The minimum setup time
for this signal is 4 HCLKs. The minimum hold time is 2 HCLKs and
the maximum hold time is 20 HCLKs. HBREQ0# should be tristated
after the hold time requirement has been satisfied.
HCPURST#
O
GTL+
CPU Reset:
The HCPURST# pin is an output from the (G)MCH. The (G)MCH
asserts HCPURST# while RSTIN# is asserted and for approximately
1 ms after RSTIN# is de-asserted. The HCPURST# allows the
processors to begin execution in a known state.
Note that the Intel®
ICH7 must provide processor frequency select
strap setup and hold times around HCPURST#. This requires strict
synchronization between (G)MCH HCPURST# de-assertion and the
ICH7 driving the straps.
HDBSY#
I/O
GTL+
Data Bus Busy:
This signal is used by the data bus owner to hold the data bus for
transfers requiring more than one cycle.
HDEFER#
O
GTL+
Defer:
HDEFER# indicates that the (G)MCH will terminate the transaction
currently being snooped with either a deferred response or with a
retry response.
Host Interface Signals (Continued)
Signal Name Type Description
HDRDY#
I/O
GTL+
Data Ready:
This signal is asserted for each cycle that data is transferred.
HEDRDY# O
GTL+
Early Data Ready:
This signal indicates that the data phase of a read transaction will start
on the bus exactly one common clock after assertion.
HDINV[3:0]# I/O
GTL+
Dynamic Bus Inversion:
These signals are driven along with the HD[63:0] signals. They
indicate if the associated signals are inverted or not.
HDINV[3:0]# are asserted such that the number of data bits driven
electrically low (low voltage) within the corresponding 16 bit group
never exceeds 8..
HDINV[x]# Data Bits
HDINV3# HD[63:48]
HDINV2# HD[47:32]
HDINV1# HD[31:16]
HDINV0# HD[15:0]
HA[31:3]#
I/O
GTL+
Host Address Bus:
HA[31:3]# connect to the processor address bus.
During processor cycles, the HA[31:3]# are inputs. The (G)MCH
drives HA[31:3]# during snoop cycles on behalf of DMI and PCI
Express* initiators.
HA[31:3]# are transferred at 2x rate.
HADSTB[1:0]# I/O
GTL+
Host Address Strobe:
These signals are the source synchronous strobes used to transfer
HA[31:3]# and HREQ[4:0] at the 2x transfer rate.
HD[63:0]#
I/O
GTL+
Host Data:
These signals are connected to the processor data bus. Data on
HD[63:0] is transferred at 4x rate. Note that the data signals may be
inverted on the processor bus, depending on the HDINV[3:0]#
signals.
HHIT#
I/O
GTL+
Hit:
This signal indicates that a caching agent holds an unmodified version
of the requested line. In addition, HHIT# is driven in conjunction with
HHITM# by the target to extend the snoop window.
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