Service manual

8224 N/B Maintenance
8224 N/B Maintenance
99
5.2 Intel ICH7-M South Bridge (10)
Functional Strap Definitions
Signal
Usage When Sampled Description
GNT3#
Top-Block
Swap Override
Rising Edge of
PWROK
The signal has a weak internal pull-up. If the
signal is sampled low, this indicates that the
system is strapped to the “top-block swap” mode
(Intel
® ICH7 inverts A16 for all cycles targeting
FWH BIOS space). The status of this strap is
readable via the Top Swap bit (Chipset Config
Registers:Offset 3414h:bit 0). Note that software
will not be able to clear the Top-Swap bit until
the system is rebooted without GNT3# being
pulled down.
GNT2#
Reserved This signal has a weak internal pull-up.
NOTE:
This signal should not be pulled low.
REQ[4:1]#
XOR Chain
Selection
Rising Edge of
PWROK
See Chapter 25 for functionality information.
LINKALER
T#
Reserved This signal requires an external pull-up resistor.
SPKR
No Reboot Rising Edge of
PWROK
The signal has a weak internal pull-down. If the
signal is sampled high, this indicates that the
system is strapped to the “No Reboot” mode
(ICH7 will disable the TCO Timer system reboot
feature). The status of this strap is readable via
the NO REBOOT bit (Chipset Config
Registers:Offset 3410h:bit 5).
INTVRMEN
Integrated
VccSus1_05
VRM Enable/
Disable
Always Enables integrated VccSus1_05 VRM when
sampled high.
EE_CS
Reserved This signal has a weak internal pull-down.
NOTE:
This signal should not be pulled high.
EE_DOUT
Reserved This signal has a weak internal pull-up.
NOTE:
This signal should not be pulled low.
GNT5#/
GPIO17#,
GNT4#/
GPIO48
Boot BIOS
Destination
Selection
Rising Edge of
PWROK
This field determines the destination of accesses
to the BIOS memory range. Signals have weak
internal pull-ups.Also controllable via Boot
BIOS Destination bit (Chipset Config
Registers:Offset 3410h:bit 11:10)
(GNT5# is MSB)
01-SPI
10-PCI
11-LPC
Direct Media Interface Signals
Name Type Description
DMI[0:3]TXP,
DMI[0:3]TXN
O
Direct Media Interface Differential Transmit Pair 0:3
DMI[0:3]RXP,
DMI[0:3]RXN
I
Direct Media Interface Differential Receive Pair 0:3
DMI_ZCOMP
O
Impedance Compensation Input:
Determines DMI input impedance.
DMI_IRCOMP
I
Impedance/Compensation Compensation Output:
Determines DMI output impedance and bias current.
Functional Strap Definitions (Continued)
Signal
Usage When Sampled Description
ACZ_SDOU
T
XOR Chain
Entrance/PCI
Express* Port
Config bit 1
Rising Edge of
PWROK
Allows entrance to XOR Chain testing when TP3
pulled low at rising edge of PWROK. See
Chapter 25 for XOR Chain functionality
information.
When TP3 not pulled low at rising edge of
PWROK, sets bit 1 of RPC.PC (Chipset Config
Registers:Offset 224h). See Section 7.1.34 for
details.
This signal has a weak internal pull-down.
ACZ_SYNC
PCI Express
Port Config
b
it
0
Rising Edge of
PWROK
This signal has a weak internal pull-down.
Sets bit 0 of RPC.PC (Chipset Config
Registers:Offset 224h). See Section 7.1.34 for
details.
GPIO25
Reserved Rising Edge of
RSMRST#
This signal has a weak internal pull-up.
NOTE:
This signal should not be pulled low.
GPIO16
Reserved This signal has a weak internal pull-down.
NOTE:
This signal should not be pulled high.
SATALED#
Reserved This signal has a weak internal pull-up enabled
only when PLTRST# is asserted.
NOTE:
This signal should not be pulled low.
TP3
XOR Chain
Entrance
Rising Edge of
PWROK
See Chapter 25 for functionality information.
This signal has a weak internal pull-up.
NOTE:
This signal should not be pulled low
unless using XOR Chain testing.
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