User Guide

8081
8081
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80
5.2 Intel 82855GM Graphics and Memory Controller Hub (GMCH)
Hub Interface Signals
Signal Name Type Description
HI_[10:0]
I/O
Hub
Packet Data: Data signals used for HI read and write operations.
HI_STB
I/O
Hub
Packet Strobe: One of two differential strobe signals used to
transmit or receive packet data over HI.
HI_STB#
I/O
Hub
Packet Strobe Complement: One of two differential strobe signals
used to transmit or receive packet data over HI.
Clock Signals
Signal Name Type Description
Host Processor Clocking
BC.LK
BCLK#
I
CMOS
Differential Host Clock In: These pins receive a buffered host
clock from the external clock synthesizer. This clock is used by all
of the GMCH logic that are in the Host clock domain (Host, Hub
and System Memory). The clock is also the reference clock for the
graphics core PLL. This is a low voltage differential input.
System Memory Clocking
SCK[5:0]
O
SSTL_2
Differential DDR SDRAM Clock: SCK and SCK# pairs are
differential clock outputs. The crossing of the positive edge of SCK
and the negative edge of SCK# is used to sample the address and
control signals on the DDR SDRAM. There are 3 pairs to each
SO-DIMM.
NOTE: ECC error detection is supported by the SCK[2] and
SCK[5] signals.
SCK[5:0]#
O
SSTL_2
Complementary Differential DDR SDRAM Clock: These are the
complimentary differential DDR SDRAM clock signals.
NOTE: ECC error detection is supported by the SCK[2]# and
SCK[5]# signals.
DVO/Hub Input Clocking
GCLKIN
I
CMOS
Input Clock: 66-MHz, 3.3-V input clock from external buffer
DVO/Hub Interface.
DVO Clocking
DVOBC.LK
DVOBCLK#
O
DVO
Differential DVO Clock Output: These pins provide a differential
pair reference clock that can run up to 165-MHz.
DVOBCLK corresponds to the primary clock out.
DVOBCLK# corresponds to the primary complementary clock out.
DVOBCLK and DVOBCLK# should be left as NC (“Not
Connected”) if the DVO B port is not implemented.
Clock Signals (Cotinued)
Signal Name Type Description
DVOCC.LK
DVOCCLK#
O
DVO
Differential DVO Clock Output: These pins provide a differential
pair reference clock that can run up to 165-MHz.
DVOCCLK corresponds to the primary clock out.
DVOCCLK# corresponds to the primary complementary clock out.
DVOCCLK and DVOCCLK# should be left as NC (“Not
Connected”) if the DVO C port is not implemented.
DVOBCCLKINT
I
DVO
DVOBC Pixel Clock Input/Interrupt: This signal may be selected
as the reference input to either dot clock PLL (DPLL) or may be
configured as an interrupt input. A TV-out device can provide the
clock reference. The maximum input frequency for this signal is 85
-MHz.
DVOBC Pixel Clock Input: When selected as the dot clock PLL
(DPLL) reference input, this clock reference input supports SSC
clocking for DVO LVDS devices.
DVOBC Interrupt: When configured as an interrupt input, this
interrupt can support either DVOB or DVOC.
DVOBCCLKINT needs to be pulled down if the signal is NOT
used.
DPMS
I
DVO
Display Power Management Signaling: This signal is used only in
mobile systems to act as the DREFCLK in certain power
management states(i.e. Display Power Down Mode); DPMS Clock
is used to refresh video during S1-M. Clock Chip is powered down
in S1-M. DPMS should come from a clock source that runs during
DAC Clocking
DREFCLK
I
LVTTL
Display Clock Input: This pin is used to provide a 48-MHz input
clock to the Display PLL that is used for 2D/Video and DAC.
LVDS LCK Flat Panel Clocking
DREFSSCLK
I
LVTTL
Display SSC Clock Input: This pin provides a 48-MHz or 66-MHz
input clock (SSC or non-SSC) to the Display PLL B.
Dedicated LVDS LCD Flat Panel Interface Signals
Signal Name Type Voltage Description
ICLKAP
O
LVDS
1.25 V±
225 mV
Channel A differential clock pair output (true): 245-800 MHz
ICLKAM
O
LVDS
1.25 V±
225 mV
Channel A differential clock pair output (compliment):
245-800 MHz.
IYAP[3:0]
O
LVDS
1.25 V±
225 mV
Channel A differential data pair 3:0 output (true): 245-800
MHz.
IYAM[3:0]
O
LVDS
1.25 V±
225 mV
Channel A differential data pair 3:0 output (compliment):
245-800 MHz.