User Guide

8081
8081
N/B Maintenance
N/B Maintenance
11
- AGTL+ bus driver technology with integrated GTL termination resistors and low voltage operation (1.05V)
- Supports Enhanced Intel
®
SpeedStep
TM
Technology (EIST) and Geyserville III
- Support for DPWR# signal to Banias processor for PSB power management
Memory System
- Directly supports one DDR channel, 64-bts wide (72-b with ECC).
- Supports 200-MHz and 266-MHz DDR devices with max of 2 Double-Sided SO-DIMMs(4 rows populated)
with unbuffered PC1600/PC2100 DDR(with ECC).
- Supports 128-Mb, 256-Mb and 512-Mbit technologies providing maximum capacity of 1-GB with only x 16 devices.
- All supported devices have 4 banks.
- Supports up to 16 simultaneous open pages.
- Supports page sizes of 2KB, 4KB, 8KB, and 16KB. Page size is individually selected for every row.
- UMA support only.
System interrupt
- Supports 8259 and Processor System Bus interrupt delivery mechanism
- Supports interrupts signaled as upstream Memory Writes from PCI and Hub interface
- MSI sent to the CPU through the system Bus
- From IOxAPIC in ICH4-M
- Provides redirection for upstream interrupts to the System Bus
- Video Stream Decoder
- Improved HW Motion Compensation for MPEG2
- All format decoder (18 ATSC formats) supported
- Dynamic Bob and Weave support for Video Streams