User Guide

8081
8081
N/B Maintenance
N/B Maintenance
104
8.2 No Display
****** System Clock Check ******
3
2
X501
14.318MHz
C622
33P
C610
33P
3
2
4
1
U512
Clock
Generator
ICS950810
P4
U504
CPU
Pentium-M
45
44
U502
Memory
Controller
Montara-GM
U10
Super I/O
HCLK_CPU
R608 33
R609 33
R606 33
49
48
21
HCLK_MCH
HCLK_MCH#
66M_MCH
P3
P5
P6
P19
HCLK_CPU#
U9
I/O
Controller
Hub
ICH4-M
P11
+3V
L515
120Z/100M
L526
120Z/100M
L523
120Z/100M
L521
120Z/100M
+3VCLKPCI
+3VCLKANA
+3VCLK66
46,50
8,14
+3VCLKCPU
1,26,37
19,32
28
VTT_PWRGD#
R629 33
R607 33
CLK_DDR[3:4], CLK_DDR[3:4]#
CLK_DDR[0:2], CLK_DDR[0:2]#
SMBDATA
SMBCLK
J503
29
30
39
22
7
56
R630 33
R601 22
R627 33
R615 33
R628 33
R610 3338
66M_ICH
PCICLK_ICH
14M_ICH
USBCLK_ICH
48M_SUPERIO
PCICLK_LPC
8
20
43
U521
PCMCIA
Controller
P18
U517
LAN Controller
P16
P17
R87
33
PCICLK_MINIPCI
J502
MiniPCI
Connector
R86
33
R85
33
12
13
PCICLK_CARD
PCICLK_LAN
115
R588 8.2K
R633 10K
MULTSEL0
R592 33
39
48M_DREFCLK
SMBDATA
SMBCLK
R159
10K
Q19
2N7002
G
S
D
Q20
2N7002
G
S
D
SMB_DATA
SMB_CLK
R172
10K
+3V
R157
2.2K
R173
2.2K
VDD3
DDR SO-DIMM
P10
10
11
FS2
x
x
x
x
Mid
Mid
Mid
Mid
FS1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
CPU
166.66
100.00
200.00
133.33
Tristate
TCLK/2
Reserved
Reserved
3V66[5:0]
66.66
66.66
66.66
66.66
Tristate
TCLK/2
Reserved
Reserved
PCI
33.33
33.33
33.33
33.33
Tristate
TCLK/2
Reserved
Reserved
0 : 0V
1 : 3.3V
UNIT : MHz
R626
4.7K
+3V
54
FS0
FS1
FS2
55
40
R621
4.7K
R613
4.7K
001 
R634
0
CORE_CLKEN#
U1~U4
U507~U510
On Board DDR
P8
P7