Operating instructions

GUIDE TO INSTALLATION AND OPERATION
14 | FRS-1801
To perform a glitch-free switch between two sources, they must be in the same clean switch region. A clean
switch region is contained within ± ½ line about an H=0 point in the reference signal, as shown by the dotted
lines in the figure. There is a clean switch region centered on every H interval. As you can see, vertical
alignment with the reference is not important for the deglitcher to operate properly.
You may switch between signals A, B or C, without any glitch, and also between signals DÙE and signals
FÙG. Any other transition, like AÙD, will cause a vertical image shift for one frame.
To determine whether a clean hot switch is possible, you need to determine whether the two input signals lie
in the same clean switch region. There are two ways to measure the position of the signals with respect to
the reference:
• Use the deglitcher tab in iControl (InputÆDeglitcher)
• Use the controller menu in Appendix 2 (videoÆtimingÆin timing to ref).
When the deglitcher mode is on, each of these sources will display the alignment offset between the
reference signal and the input signal. Knowing the offset for both input signals, you can determine if they are
in the same clean switch region. If so, any hot-switch between those two signals will be glitch less.
To determine the limits of a clean switch region, you must know the input’s line length in μs. The first region
is delimited by +½ line and -½ line of the reference. For example, with an SD (525) signal the line length is
63.5 μs and so the first region lies between -31.76 μs and 31.76 μs. Other regions can be found by adding or
removing a multiple of line length to the two boundaries.
Example: for an SD (525) input signal, we have these clean switch regions:
-1 line and -31.76 μs to 0 line and -31.76 μs
0 line and -31.76 μs to 0 line and 31.76 μs
0 line and 31.76 μs to 1 line and 31.76 μs
etc.
Practical examples:
Example 1: we have two SD (525) sources, one that indicates an offset of -25 μs with respect to the
reference (A) and the other an offset of -35 μs (B). We know that a clean switch region limit is present at -½