Product Manual

© MiMOMax Wireless Ltd
Tornado Product Manual
14
3.2 DIGITAL PROCESSING SYSTEM
The DPS is the heart of the radio unit. It provides an accurate and stable 40MHz system reference clock from which all the
required digital clocks and RF local oscillator frequencies for transmit and receive functions are derived. It processes signals
that have been transmitted or received and provides overall control and monitoring to the rest of the system via the built-in
Configuration, Control and Management Software CCMS software. Power supplies are also provided by the DPS.
3.2.1 Power supply
The power supply operates off a 10.5 to 60 VDC input and generates stable 13.5V, 5.4V, 5.0V, 3.3V, 2.5V,1.8V 1.2V and 18V
internal power supply rails, that all the other circuitry runs off. The input of the power supply is isolated from the rest of the
circuitry and the chassis. Input voltage monitoring is provided via CCMS.
3.2.2 Central Processor Unit
An ARM Cortex A8 based microcontroller is used as the CPU in the DPS board. It uses a reference clock of 26MHz. The CPU
provides external device connectivity through the built-in and external peripherals.
The CPU runs a Linux embedded operating system which provides various services such as scheduling, process
management, memory management, device and resource management, TCP/IP stacks and inter-networking, applications,
user interface, system configuration and control etc. An integral part of the Linux operating system is the MiMOMax specific
network driver, which configures the radio unit as a standard Ethernet device.
3.2.3 FPGA
An Altera Cyclone IV Field Programmable Gate Array is used to implement the physical layer TX and Rx signal processing,
MAC layer and signalling protocols on the serial interfaces.
3.2.4 Receive Converters
The 45.1MHz analogue IF signals from each receiver channel are fed to a dual 10-bit ADC. The signals are sampled using a
40MHz clock which is generated from the 40MHz system reference clock. The digital outputs from the ADC are fed to the
FPGA for processing.
3.2.5 Transmit Converters
The digital transmit signals from the FPGA are fed to a dual 14-bit DAC which uses a clock frequency of 40MHz to produce
the analogue IF signal for each transmitter channel. The IF output is 15.3835MHz. This is chosen in conjunction with the
transmitter local oscillator frequency to minimise the generation of spurious frequencies in the transmitted RF output spectrum.
3.2.6 Reference & Clock Synthesisers
The main system reference clock consists of a low-noise, voltage-controlled, temperature-compensated, crystal oscillator
(VCTCXO) operating at 40MHz. Factory calibration of this oscillator against an external GPS or other frequency reference is
provided by means of a non-volatile sample-and-hold facility which adjusts the VCTCXO DC control voltage to set the
frequency precisely to 40.0MHz. The VCTCXO may also be phase-locked to an external 10 MHz reference if required. If the
external reference input is not in use the internal reference divided down to 10 MHz can be provided as an output. External
reference in/out is provided via an isolated differential connection on the GPIO connector.
The 40MHz output from the VCTCXO is buffered and distributed to provide low-noise differential reference signals for the
transmitter and receiver local oscillators, transmit DACs, receive ADCs and the FPGA.
The 40MHz output from the VCTCXO also feeds a PLL IC which generates a 26MHz clock for the CPU and a 25MHz clock
for the Ethernet controller IC.
3.2.7 Dual Ethernet
The Ethernet is provided via a three-port managed Ethernet switch, one port is the internal connection to the CPU, and the
other two ports are available on the RJ45 connectors labelled ‘Eth1’ and ‘Eth2’ on the front panel. The Ethernet ports are both
10/100BASE-Tx ports, supporting full and half duplex, flow control, auto MDI-X and auto negotiation.