Specifications

mikroElektronika | Free Online Book | PIC Microcontrollers | Chapter 6: Serial Communication Modules
device should set the ADDEN bit in order to enable new address detection.
Fig. 6-7 Sending Data
TXSTA Register
Fig.6-8 TXSTA Register
CSRC - Clock Source Select bit - determines clock source. It is used only in synchronous mode.
1 - Master mode. Clock is generated internally from Baud Rate Generator; and
0 - Slave mode. Clock is generated from external source.
TX9 - 9-bit Transmit Enable bit
1 - 9-bit data transmission via EUSART system; and
0 - 8-bit data transmission via EUSART system.
TXEN - Transmit Enable bit
1 - Transmission enabled; and
0 - Transmission disabled.
SYNC - EUSART Mode Select bit
1 - EUSART operates in synchronous mode; and
0 - EUSART operates in asynchronous mode.
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