Specifications

mikroElektronika | Free Online Book | PIC Microcontrollers | Chapter 2: Core SFRs
Fig. 2-14 PIR2 register
● OSFIF - Oscillator Fail Interrupt Flag bit.
❍ 1 - System oscillator failed and clock input has changed to internal oscillator INTOSC. This bit must be cleared
in software.
❍ 0 - System oscillator operates normally.
● C2IF - Comparator C2 Interrupt Flag bit.
❍ 1 - Comparator C2 output has changed (bit C2OUT). This bit must be cleared in software.
❍ 0 - Comparator C2 output has not changed.
● C1IF - Comparator C1 Interrupt Flag bit.
❍ 1 - Comparator C1 output has changed (bit C1OUT). This bit must be cleared in software.
❍ 0 - Comparator C1 output has not changed.
● EEIF - EE Write Operation Interrupt Flag bit.
❍ 1 - EEPROM write completed. This bit must be cleared in software.
❍ 0 - EEPROM write is not completed or has not started.
● BCLIF - Bus Collision Interrupt Flag bit.
❍ 1 - A bus collision has occurred in the MSSP when configured for I2C Master mode. This bit must be cleared in
software.
❍ 0 - No bus collision has occurred.
● ULPWUIF - Ultra Low-power Wake-up Interrupt Flag bit.
❍ 1 - Wake-up condition has occurred. This bit must be cleared in software.
❍ 0 - No Wake-up condition has occurred.
● CCP2IF - CCP2 Interrupt Flag bit.
❍ 1 - CCP2 interrupt condition has occurred (unit for capturing, comparing and generating PWM signal).
Depending on operating mode, capture or compare match has occurred. In both cases, the bit must be
cleared in software. This bit is not used in PWM mode.
❍ 0 - No CCP2 interrupt condition has occurred.
PCON register
The PCON register contains only two flag bits used to differentiate between a: power-on reset, brown-out reset, Watchdog
Timer Reset and external reset (through MCLR pin).
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