Specifications

mikroElektronika | Free Online Book | PIC Microcontrollers | Chapter 2: Core SFRs
● SSPIE - Master Synchronous Serial Port (MSSP) Interrupt Enable bit - enables an interrupt request to be generated
after each data transfer via synchronous serial communication module (SPI or I2C mode).
❍ 1 - Enables the MSSP interrupt.
❍ 0 - Disables the MSSP interrupt.
● CCP1IE - CCP1 Interrupt Enable bit enables an interrupt request to be generated in CCP1 module used for PWM
signal processing.
❍ 1 - Enables the CCP1 interrupt.
❍ 0 - Disables the CCP1 interrupt.
● TMR2IE - TMR2 to PR2 Match Interrupt Enable bit
❍ 1 - Enables the TMR2 to PR2 match interrupt.
❍ 0 - Disables the TMR2 to PR2 match interrupt.
● TMR1IE - TMR1 Overflow Interrupt Enable bit enables an interrupt request to be generated after each timer TMR1
register overflow, i.e. when the counting starts from zero.
❍ 1 - Enables the TMR1 overflow interrupt.
❍ 0 - Disables the TMR1 overflow interrupt.
PIE2 Register
The PIE2 Register also contains the various interrupt enable bits.
Fig. 2-12 PIE2 Register
● OSFIE - Oscillator Fail Interrupt Enable bit.
❍ 1 - Enables oscillator fail interrupt.
❍ 0 - Disables oscillator fail interrupt.
● C2IE - Comparator C2 Interrupt Enable bit.
❍ 1 - Enables Comparator C2 interrupt.
❍ 0 - Disables Comparator C2 interrupt.
● C1IE - Comparator C1 Interrupt Enable bit.
❍ 1 - Enables Comparator C1 interrupt.
❍ 0 - Disables Comparator C1 interrupt.
● EEIE - EEPROM Write Operation Interrupt Enable bit.
❍ 1 - Enables EEPROM write operation interrupt.
❍ 0 - Disables EEPROM write operation interrupt.
● BCLIE - Bus Collision Interrupt Enable bit.
❍ 1 - Enables bus collision interrupt.
❍ 0 - Disables bus collision interrupt.
● ULPWUIE - Ultra Low-Power Wake-up Interrupt Enable bit.
❍ 1 - Enables Ultra Low-Power Wake-up interrupt.
❍ 0 - Disables Ultra Low-Power Wake-up interrupt.
● CCP2IE - CCP2 Interrupt Enable bit.
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