Specifications

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that it does not affect interrupts triggered by the timer TMR0 or by changing state on port B or RB0/INT pin.
❍ 1 - Enables all unmasked peripheral interrupts.
❍ 0 - Disables all peripheral interrupts.
● T0IE - TMR0 Overflow Interrupt Enable bit controls interrupt enabled by TMR0 overflow.
❍ 1 - Enables the TMR0 interrupt.
❍ 0 - Disables the TMR0 interrupt.
● INTE - RB0/INT External Interrupt Enable bit controls interrupt caused by changing logic state on pin RB0/IN
(external interrupt).
❍ 1 - Enables the INT external interrupt.
❍ 0 - Disables the INT external interrupt.
● RBIE - RB Port Change Interrupt Enable bit. When configured as inputs, port B pins may cause interrupt by
changing their logic state (no matter whether it is highto- low transition or vice versa, fact that something is
changed only matters). This bit determines whether interrupt is to occur or not.
❍ 1 - Enables the port B change interrupt.
❍ 0 - Disables the port B change interrupt.
● T0IF - TMR0 Overflow Interrupt Flag bit registers the timer TMR0 register overflow, when counting starts from
zero.
❍ 1 - TMR0 register has overflowed (bit must be cleared in software).
❍ 0 - TMR0 register has not overflowed.
● INTF - RB0/INT External Interrupt Flag bit registers change of logic state on the RB0/INT pin.
❍ 1 - The INT external interrupt has occurred (must be cleared in software).
❍ 0 - The INT external interrupt has not occurred.
● RBIF - RB Port Change Interrupt Flag bit registers change of logic state of some port B input pins.
❍ 1 - At least one of the port B general purpose I/O pins has changed state. Upon reading portB, RBIF (flag bit)
must be cleared in software.
❍ 0 - None of the port B general purpose I/O pins has changed state.
PIE1 Register
The PIE1 register contains the peripheral interrupt enable bits.
Fig. 2-11 PIE1 register
● ADIE - A/D Converter Interrupt Enable bit.
❍ 1 - Enables the ADC interrupt.
❍ 0 - Disables the ADC interrupt.
● RCIE - EUSART Receive Interrupt Enable bit.
❍ 1 - Enables the EUSART receive interrupt.
❍ 0 - Disables the EUSART receive interrupt.
● TXIE - EUSART Transmit Interrupt Enable bit.
❍ 1 - Enables the EUSART transmit interrupt.
❍ 0 - Disables the EUSART transmit interrupt.
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