Specifications

mikroElektronika | Free Online Book | PIC Microcontrollers | Chapter 6: Serial Communication Modules
Since maximum 112 integrated circuits may simultaneously
share the same transmission line, the first data byte must
contain address which matches only one slave device. Each
component has its own address listed in the proper data
sheet. The eighth bit of the first data byte specifies
direction of data transmission, the microcontroller is to
send or receive data. In this case, it is all about data
receive and the eighth bit therefore is logic zero (0).
Fig. 6-28 Data Transmission in I²C Master Mode
When address match occurs,
the microcontroller has to wait
for the acknowledge data bit.
The slave device acknowledges
address match by clearing the
ASKSTAT bit of the SSPCON2
register. If the match properly
occurred, all bytes
representing data are
transmitted in the same way.
Data transmission ends by
setting the SEN bit of the
SSPCON2 register. The so
called STOP condition occurs,
which enables the SDA pin to
receive pulse condition: Start -
Address - Acknowledge - Data -
Acknowledge ....Data -
Acknowledge - Stop!
Fig.6-29 Data Transmission in
I²C Master Mode
Data Reception in I²C Master Mode
Preparations for data reception are similar to those for data transmission, with exception that the last bit of the first sent
byte (containing address) is logic one (1). It specifies that master expects to receive data from addressed slave device.
With regard to the microcontroller, the following events occur:
After internal preparations are finished and START bit is set, slave device starts sending one byte at a time. These bytes
are stored in the serial register SSPSR. Each data is, after receiving the last eighth bit, loaded to the SSPBUF register from
where it can be read. By reading this register, the acknowledge bit is automatically sent, which means that master device
is ready to receive new data.
At the end, similar to data transmission, data reception ends by setting the STOP bit:
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