Datasheet
© 2008 Microchip Technology Inc. DS39646C-page 77
PIC18F8722 FAMILY
STATUS — — —NOVZDCC---x xxxx 58, 80
TMR0H Timer0 Register High Byte 0000 0000 58, 163
TMR0L Timer0 Register Low Byte xxxx xxxx 58, 163
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 58, 161
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 39, 58
HLVDCON VDIRMAG
— IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 58, 291
WDTCON
— — — — — — —SWDTEN--- ---0 58, 313
RCON IPEN SBOREN
(1)
—RITO PD POR BOR 0q-1 11q0 50, 56,
58, 133
TMR1H Timer1 Register High Byte xxxx xxxx 58, 169
TMR1L Timer1 Register Low Byte xxxx xxxx 58, 169
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 58, 165
TMR2 Timer2 Register 0000 0000 58, 172
PR2 Timer2 Period Register 1111 1111 58, 172
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 58, 171
SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 58, 169,
170
SSP1ADD MSSP1 Address Register in I
2
C™ Slave mode. MSSP1 Baud Rate Reload Register in I
2
C Master mode. 0000 0000 58, 170
SSP1STAT SMP CKE D/A
PSR/WUA BF 0000 0000 58, 162,
171
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 58, 163,
172
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 58, 173
ADRESH A/D Result Register High Byte xxxx xxxx 59, 280
ADRESL A/D Result Register Low Byte xxxx xxxx 59, 280
ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 59, 271
ADCON1
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 59, 272
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 59, 273
CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx 59, 180
CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 59, 180
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 59, 187
CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte xxxx xxxx 59, 180
CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 59, 180
CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 59, 179
CCPR3H Enhanced Capture/Compare/PWM Register 3 High Byte xxxx xxxx 59, 180
CCPR3L Enhanced Capture/Compare/PWM Register 3 Low Byte xxxx xxxx 59, 180
CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 59, 179
ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 59, 201
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 59, 287
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 59, 289
TMR3H Timer3 Register High Byte xxxx xxxx 59, 175
TMR3L Timer3 Register Low Byte xxxx xxxx 59, 175
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 0000 0000 59, 173
TABLE 5-3: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, this bit reads as ‘0’.
2: These registers and/or bits are not implemented on 64-pin devices and are read as
‘0’. Reset values are shown for 80-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as
‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
5: RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 and LATG5 read as
‘0’.
6: Bit 7 and Bit 6 are cleared by user software or by a POR.
7: Bit 21 of TBLPTRU allows access to the device Configuration bits.