Datasheet

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PIC18F8722 FAMILY

FSR1H 6X27 6X22 8X27 8X22

---- 0000 ---- 0000

---- uuuu

FSR1L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu

BSR 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu

INDF2 6X27 6X22 8X27 8X22 N/A N/A N/A

POSTINC2 6X27 6X22 8X27 8X22 N/A N/A N/A

POSTDEC2 6X27 6X22 8X27 8X22 N/A N/A N/A

PREINC2 6X27 6X22 8X27 8X22 N/A N/A N/A

PLUSW2 6X27 6X22 8X27 8X22 N/A N/A N/A

FSR2H 6X27 6X22 8X27 8X22

---- 0000 ---- 0000

---- uuuu

FSR2L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu

STATUS 6X27 6X22 8X27 8X22 ---x xxxx ---u uuuu ---u uuuu

TMR0H 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu

TMR0L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu

T0CON 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu

OSCCON 6X27 6X22 8X27 8X22

0100 q000 0100 q000 uuuu uuqu

HLVDCON 6X27 6X22 8X27 8X22 0-00 0101 0-00 0101 u-uu uuuu

WDTCON 6X27 6X22 8X27 8X22 ---- ---0 ---- ---0 ---- ---u

RCON

(4)

6X27 6X22 8X27 8X22 0q-1 11q0 0q-q qquu uq-u qquu

TMR1H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu

TMR1L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 6X27 6X22 8X27 8X22 0000 0000 u0uu uuuu uuuu uuuu

TMR2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu

PR2 6X27 6X22 8X27 8X22 1111 1111 uuuu uuuu uuuu uuuu

T2CON 6X27 6X22 8X27 8X22 -000 0000 -000 0000 -uuu uuuu

SSP1BUF 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu

SSP1ADD 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu

SSP1STAT 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu

SSP1CON1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu

SSP1CON2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Power-on Reset,

Brown-out Reset

MCLR

Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector

(0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with

the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled

as PORTA pins, they are disabled and read ‘0’.