Datasheet

PIC18F8722 FAMILY

TABLE 28-27: A/D CONVERSION REQUIREMENTS

Param

No.

Symbol Characteristic Min Max Units Conditions

130 T

AD A/D Clock Period PIC18FXXXX 0.7 25.0

(1)

μsTOSC based, VREF ≥ 3.0V

PIC18LFXXXX 1.4 25.0

(1)

μsVDD = 2.0V;

OSC based, VREF full range

PIC18FXXXX — 1 μs A/D RC mode

PIC18LFXXXX — 3 μsVDD = 2.0V; A/D RC mode

131 T

CNV Conversion Time

(not including acquisition time) (Note 2)

11 12 TAD

132 TACQ Acquisition Time (Note 3) 1.4 — μs-40°C to +85°C

135 T

SWC Switching Time from Convert → Sample — (Note 4)

137 TDIS Discharge Time 0.2 — μs

Legend: TBD = To Be Determined

Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

2: ADRES register may be read on the following TCY cycle.

3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (V

DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.

4: On the following cycle of the device clock.