Datasheet

© 2008 Microchip Technology Inc. DS39646C-page 415
PIC18F8722 FAMILY
FIGURE 28-23: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 28-24: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 28-24: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 28-25: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
121
121
120
122
CKx/TXx
DTx/RXx
pin
pin
Note: Refer to Figure 28-5 for load conditions.
Param
No.
Symbol Characteristic Min Max Units Conditions
120 T
CKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid PIC18FXXXX — 40 ns
PIC18LFXXXX — 100 ns VDD = 2.0V
121 TCKRF Clock Out Rise Time and Fall Time
(Master mode)
PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns V
DD = 2.0V
122 TDTRF Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns VDD = 2.0V
125
126
CKx/TXx
DTx/RXx
pin
pin
Note: Refer to Figure 28-5 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 T
DTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CKx ↓ (DTx hold time) 10 — ns
126 T
CKL2DTL Data Hold after CKx ↓ (DTx hold time) 15 — ns