Datasheet

PIC18F8722 FAMILY
DS39646C-page 408 © 2008 Microchip Technology Inc.
FIGURE 28-16: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE =
1)
SSx
SCKx
(CKP =
0)
SCKx
(CKP =
1)
SDOx
SDIx
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
LSb
Note: Refer to Figure 28-5 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
71 T
SCH SCKx Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 T
SCL SCKx Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TDIV2SCH,
T
DIV2SCL
Setup Time of SDIx Data Input to SCKx Edge 20 — ns
73A T
B2B Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
1.5 TCY + 40 — ns (Note 2)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDIx Data Input to SCKx Edge 40 — ns
75 TDOR SDOx Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns V
DD = 2.0V
76 T
DOF SDOx Data Output Fall Time — 25 ns
78 T
SCR SCKx Output Rise Time
(Master mode)
PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns V
DD = 2.0V
79 T
SCF SCKx Output Fall Time (Master mode) — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDOx Data Output Valid after
SCKx Edge
PIC18FXXXX — 50 ns
PIC18LFXXXX — 100 ns V
DD = 2.0V
81 T
DOV2SCH,
T
DOV2SCL
SDOx Data Output Setup to SCKx Edge T
CY —ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.