Datasheet

PIC18F8722 FAMILY
DS39646C-page 406 © 2008 Microchip Technology Inc.
FIGURE 28-14: PARALLEL SLAVE PORT TIMING (PIC18F8527/8622/8627/8722)
TABLE 28-15: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8527/8622/8627/8722)
Note: Refer to Figure 28-5 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
Param.
No.
Symbol Characteristic Min Max Units Conditions
62 TdtV2wrH Data In Valid before WR
↑ or CS ↑ (setup time) 20 — ns
63 TwrH2dtI WR
↑ or CS ↑ to Data–In
Invalid (hold time)
PIC18FXXXX 20 — ns
PIC18LFXXXX 35 — ns VDD = 2.0V
64 TrdL2dtV RD
↓ and CS ↓ to Data–Out Valid — 80 ns
65 TrdH2dtI RD
↑ or CS ↓ to Data–Out Invalid 10 30 ns
66 TibfINH Inhibit of the IBF Flag bit being Cleared from
WR
↑ or CS ↑
—3 T
CY