Datasheet

© 2008 Microchip Technology Inc. DS39646C-page 317
PIC18F8722 FAMILY
25.5 Program Verification and
Code Protection
The user program memory is divided into four blocks
for PIC18F6527/8527 devices, five blocks for
PIC18F6622/8622 devices, six blocks for PIC18F6627/
8627 devices and eight blocks for PIC18F6722/8722
devices. One of these is a boot block of 2, 4 or
8 Kbytes. The remainder of the memory is divided into
blocks on binary boundaries.
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 25-5 shows the program memory organization for
48, 64, 96 and 128-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 25-3.
FIGURE 25-5: CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F8722 FAMILY
000000h
200000h
3FFFFFh
01FFFFh
Note: Sizes of memory areas are not to scale.
* Boot block size is determined by the BBSIZ<1:0> bits in CONFIG4L.
Code Memory
Unimplemented
Read as ‘
0’
Configuration
and ID
Space
MEMORY SIZE/DEVICE
128 Kbytes
(PIC18FX722)
96 Kbytes
(PIC18FX627)
64 Kbytes
(PIC18FX622)
48 Kbytes
(PIC18FX527)
Address
Range
Boot Block Boot Block Boot Block Boot Block
000000h
0007FFh* or
000FFFh* or
001FFFh*
Block 0 Block 0 Block 0 Block 0
000800h* or
001000h* or
002000h*
003FFFh
Block 1 Block 1 Block 1 Block 1
004000h
007FFFh
Block 2 Block 2 Block 2 Block 2
008000h
00BFFFh
Block 3 Block 3 Block 3
Unimplemented
Read ‘
0’s
00C000h
00FFFFh
Block 4 Block 4
Unimplemented
Read ‘
0’s
010000h
013FFFh
Block 5 Block 5
014000h
017FFFh
Block 6
Unimplemented
Read ‘
0’s
018000h
01BFFFh
Block 7
01C000h
01FFFFh