Datasheet

PIC18F8722 FAMILY
DS39646C-page 304 © 2008 Microchip Technology Inc.
REGISTER 25-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1 R/P-0 R/P-0 R/P-0 U-0 R/P-1 U-0 R/P-1
DEBUG
XINST BBSIZ1 BBSIZ0 —LVP —STVREN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 DEBUG
: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6 XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
bit 5-4 BBSIZ<1:0>: Boot Block Size Select bits
11 = 4K words (8 Kbytes) boot block size
10 = 4K words (8 Kbytes) boot block size
01 = 2K words (4 Kbytes) boot block size
00 = 1K word (2 Kbytes) boot block size
bit 3 Unimplemented: Read as ‘0’
bit 2 LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
bit 1 Unimplemented: Read as ‘0’
bit 0 STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset