Datasheet

© 2008 Microchip Technology Inc. DS39646C-page 265
PIC18F8722 FAMILY
FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60
PIE1
PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60
IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60
TRISG
— — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59
TXREGx EUSARTx Transmit Register 59
TXSTAx CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D 59
BAUDCONx ABDOVF RCIDL —SCKPBRG16— WUE ABDEN 61
SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61
SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
DTx pin
CKx pin
Write to
TXREGx reg
TXxIF bit
TRMT bit
bit 0
bit 1
bit 2
bit 6 bit 7
TXEN bit