Datasheet

© 2008 Microchip Technology Inc. DS39646C-page 261
PIC18F8722 FAMILY
FIGURE 20-7: ASYNCHRONOUS RECEPTION
TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60
PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60
IPR1
PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60
TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59
RCREGx EUSARTx Receive Register 59
TXSTAx
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59
BAUDCONx ABDOVF RCIDL
— SCKP BRG16 — WUE ABDEN 61
SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61
SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Start
bit
bit 7/8
bit 1bit 0 bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RXx (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREGx
Word 2
RCREGx
Stop
bit
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (receive buffer) is read after the third word
causing the OERR (Overrun) bit to be set.