Datasheet

PIC18F8722 FAMILY
DS39646C-page 204 © 2008 Microchip Technology Inc.
TABLE 18-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
RCON IPEN
SBOREN — RI TO PD POR BOR 58
PIR1
PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60
PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60
IPR1
PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60
PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60
PIE2
OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60
IPR2 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 60
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 60
TRISG
— — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60
TRISH
(2)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 60
TMR1L Timer1 Register Low Byte 58
TMR1H Timer1 Register High Byte 58
T1CON RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 58
TMR2 Timer2 Register 58
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 58
PR2 Timer2 Period Register 58
TMR3L Timer3 Register Low Byte 59
TMR3H Timer3 Register High Byte 59
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 59
TMR4 Timer4 Register 61
T4CON
— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 61
PR4 Timer4 Period Register 61
CCPRxL
(1)
Enhanced Capture/Compare/PWM Register x Low Byte 59, 61
CCPRxH
(1)
Enhanced Capture/Compare/PWM Register x High Byte 59, 61
CCPxCON
(1)
PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 59
ECCPxAS
(1)
ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 59, 61
ECCPxDEL
(1)
PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: Generic term for all of the identical registers of this name for all Enhanced CCP modules, where ‘x’ identifies the
individual module (ECCP1, ECCP2 or ECCP3). Bit assignments and Reset values for all registers of the same
generic name are identical.
2: This register is not implemented on PIC18F6527/6622/6627/6722 devices.