Datasheet

PIC18F8722 FAMILY
DS39646C-page 182 © 2008 Microchip Technology Inc.
17.3 Compare Mode
In Compare mode, the 16-bit value of the CCPRx
registers is constantly compared against either the
TMR1 or TMR3 register pair value. When a match
occurs, the CCPx pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCPxM<3:0>). At the same time, the
interrupt flag bit, CCPxIF, is set.
17.3.1 CCPx PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
17.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
17.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the corresponding CCPx pin is
not affected. Only a CCP interrupt is generated, if
enabled and the CCPxIE bit is set.
17.3.4 SPECIAL EVENT TRIGGER
All CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM<3:0> = 1011).
For all CCP modules, the Special Event Trigger resets
the timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
The ECCP2 Special Event Trigger can also start an A/D
conversion. In order to do this, the A/D converter must
already be enabled.
FIGURE 17-3: COMPARE MODE OPERATION BLOCK DIAGRAM
Note: Clearing the CCPxCON register will force
the compare output latch (depending on
device configuration) to the default low
level. This is not the port I/O data latch.
CCPR4H CCPR4L
TMR1H TMR1L
Comparator
QS
R
Output
Logic
Special Event Trigger
Set Flag bit CCP4IF
Match
RG3/CCP4 pin
TRISG<3>
CCP4CON<3:0>
Mode Select
Output Enable
TMR3H TMR3L
T3CCP2
1
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