Datasheet

PIC18F8722 FAMILY
DS39646C-page 152 © 2008 Microchip Technology Inc.
TABLE 11-13: PORTG FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RG0/ECCP3/P3A RG0 0 O DIG LATG<0> data output.
1 I ST PORTG<0> data input.
ECCP3 0 O DIG ECCP3 compare and ECCP3 PWM output. Takes priority over
port data.
1 I ST ECCP3 capture input.
P3A 0 O DIG ECCP3 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RG1/TX2/CK2 RG1 0 O DIG LATG<1> data output.
1 I ST PORTG<1> data input.
TX2 0 O DIG Asynchronous serial transmit data output (EUSART2 module). Takes
priority over port data.
CK2 0 O DIG Synchronous serial clock output (EUSART2 module). Takes priority
over port data.
1 I ST Synchronous serial clock input (EUSART2 module).
RG2/RX2/DT2 RG2 0 O DIG LATG<2> data output.
1 I ST PORTG<2> data input.
RX2 1 I ST Asynchronous serial receive data input (EUSART2 module).
DT2 1 O DIG Synchronous serial data output (EUSART2 module). Takes priority
over port data. User must configure as an input.
1 I ST Synchronous serial data input (EUSART2 module). User must
configure as an input.
RG3/CCP4/P3D RG3 0 O DIG LATG<3> data output.
1 I ST PORTG<3> data input.
CCP4 0 O DIG CCP4 compare and PWM output; takes priority over port data and
P3D function.
1 I ST CCP4 capture input.
P3D 0 O DIG ECCP3 Enhanced PWM output, channel D. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RG4/CCP5/P1D RG4 0 O DIG LATG<4> data output.
1 I ST PORTG<4> data input.
CCP5 0 O DIG CCP5 compare and PWM output. Takes priority over port data and
P1D function.
1 I ST CCP5 capture input.
P1D 0 O DIG ECCP1 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RG5/MCLR
/VPP RG5 —
(1)
I ST PORTG<5> data input; enabled when MCLRE Configuration bit
is clear.
MCLR
— I ST External Master Clear input; enabled when MCLRE Configuration
bit is set.
V
PP — I ANA High-voltage detection; used for ICSP™ mode entry detection.
Always available regardless of pin mode.
Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: RG5 does not have a corresponding TRISG bit.