Datasheet

© 2008 Microchip Technology Inc. DS39646C-page 109
PIC18F8722 FAMILY
7.7 Operation in Power-Managed
Modes
In alternate power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if wait states have
been enabled and added to external memory opera-
tions. If operations in a lower power Run mode are
anticipated, users should provide in their applications
for adjusting memory access times at the lower clock
speeds.
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are sus-
pended. The state of the external bus is frozen with the
address/data pins and most of the control pins holding
at the same state they were in when the mode was
invoked. The only potential changes are the CE
, LB
and UB pins which are held at logic high.
TABLE 7-3: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-MANAGED MODES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
MEMCON
(1)
EBDIS —WAIT1WAIT0— —WM1WM060
CONFIG3L
(2)
WAIT BW ABW1 ABW0 — —PM1PM0302
CONFIG3H MCLRE — — — — LPT1OSC ECCPMX
(2)
CCP2MX 303
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the External Memory Bus.
Note 1: This register is not implemented on 64-pin devices.
2: Unimplemented in PIC18F6527/6622/6627/6722 devices.