Datasheet

© 2008 Microchip Technology Inc. DS39646C-page 107
PIC18F8722 FAMILY
7.6.1 8-BIT MODE TIMING
The presentation of control signals on the External
Memory Bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-8 through Figure 7-11.
FIGURE 7-8: EXTERNAL BUS TIMING FOR TBLRD (MICROPROCESSOR MODE)
FIGURE 7-9: EXTERNAL BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE)
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
Q2Q1 Q3 Q4
AD<15:8>,
ALE
OE
AAh
WRH
WRL
AD<7:0>
03Ah 03Ah
BA0
Opcode Fetch Opcode Fetch Opcode Fetch
TBLRD *
TBLRD Cycle 1
ADDLW 55h
from 007554h
08h
‘
1’
Q2Q1 Q3 Q4
CCFh
33h
Table Read 92h
from 199E67h
92h
‘
1’
00h ABh 55h 0Eh ACh 55h 0Fh
03Ah
‘1’
‘
1’
from 007558h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRD Cycle 2
MOVLW 55h
from 007556h
MOVLW
A<19:16>
(1)
Note 1: The address lines actually used depends on the address width selected. This example assumes 20-bit addressing.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
Q2Q1 Q3 Q4
A<19:16>
(1)
ALE
OE
AD<7:0>
CE
Opcode Fetch Opcode Fetch Opcode Fetch
TBLRD *
TBLRD Cycle 1
ADDLW 55h
from 000100h
Q2Q1 Q3 Q4
0Ch
33h
TBLRD 92h
from 199E67h
92h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRD Cycle 2
MOVLW 55h
from 000102h
MOVLW
AD<15:8>
(1)
CFh
Note 1: The address lines actually used depends on the address width selected. This example assumes 20-bit addressing.