Datasheet

PIC18F87J50 FAMILY
DS39775C-page 88 © 2009 Microchip Technology Inc.
UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP6
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP5
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP4
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP3
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP2
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP1
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP0
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
PMCONH PMPEN
— PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 0-00 0000 66, 168
PMCONL CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP 0000 0000 67, 169
PMMODEH BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 0000 0000 67, 170
PMMODEL WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000 0000 67, 171
PMDOUT2H Parallel Port Out Data High Byte (Buffer 3) 0000 0000 67, 174
PMDOUT2L Parallel Port Out Data Low Byte (Buffer 2) 0000 0000 67, 174
PMDIN2H Parallel Port In Data High Byte (Buffer 3) 0000 0000 67, 174
PMDIN2L Parallel Port In Data Low Byte (Buffer 2) 0000 0000 67, 174
PMEH PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 0000 0000 67, 171
PMEL PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000 0000 67, 172
PMSTATH IBF IBOV
— — IB3F IB2F IB1F IB0F 00-- 0000 67, 172
PMSTATL OBE OBUF
— — OB3E OB2E OB1E OB0E 10-- 1111 67, 173
TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs.
Note 1: Bit 21 of the PC is only available in Serial Programming modes.
2: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
4: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
5: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
6: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 19.4.3.2 “Address
Masking Modes” for details
7: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
8: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.