Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 87
PIC18F87J50 FAMILY
CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 65, 210
CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 65, 210
CCP4CON
— — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 65, 210
CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 65, 210
CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 65, 210
CCP5CON
— — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 65, 210
SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 65, 243,
278
SSP2ADD/ MSSP2 Address Register (I
2
C™ Slave mode), MSSP2 Baud Rate Reload Register (I
2
C Master mode) 0000 0000 65, 243
SSP2MSK
(5)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 0000 0000 65, 250
SSP2STAT SMP CKE D/A
PSR/WUA BF 1111 1111 65, 233,
244
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 65, 233,
245
SSP2CON2
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 65, 233,
245
GCEN
ACKSTAT ADMSK5
(6)
ADMSK4
(6)
ADMSK3
(6)
ADMSK2
(6)
ADMSK1
(6)
SEN
CMSTAT
— — — — — — COUT2 COUT1 ---- --11 65, 339
PMADDRH/ CS2 CS1 Parallel Master Port Address High Byte 0000 0000 66, 174
PMDOUT1H
(8)
Parallel Port Out Data High Byte (Buffer 1) 0000 0000 66, 177
PMADDRL/ Parallel Master Port Address Low Byte 0000 0000 66, 174
PMDOUT1L
(8)
Parallel Port Out Data Low Byte (Buffer 0) 0000 0000 66, 174
PMDIN1H Parallel Port In Data High Byte (Buffer 1) 0000 0000 66, 174
PMDIN1L Parallel Port In Data Low Byte (Buffer 0) 0000 0000 66, 174
UCON
— PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- 66, 312
USTAT
— ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx- 66, 316
UEIR BTSEF
— — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 66, 329
UIR
— SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 66, 326
UFRMH
— — — — — FRM10 FRM9 FRM8 ---- -xxx 66, 318
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 66, 318
UCFG UTEYE
— — UPUEN UTRDIS FSEN PPB1 PPB0 00-0 0000 66, 313
UADDR
— ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 66, 318
UEIE BTSEE
— — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 66, 330
UIE
— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 66, 328
UEP15
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP14
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP13
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP12
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP11
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP10
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP9
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
UEP8
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317
TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs.
Note 1: Bit 21 of the PC is only available in Serial Programming modes.
2: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
4: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
5: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
6: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 19.4.3.2 “Address
Masking Modes” for details
7: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
8: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.