Datasheet

PIC18F87J50 FAMILY
DS39775C-page 84 © 2009 Microchip Technology Inc.
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 62, 91
STATUS
— — —NOVZDCC---x xxxx 62, 89
TMR0H Timer0 Register High Byte 0000 0000 62, 193
TMR0L Timer0 Register Low Byte xxxx xxxx 62, 193
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 62, 192
OSCCON
(2)
/ IDLEN IRCF2 IRCF1 IRCF0 OSTS
(4)
— SCS1 SCS0 0110 q100 62, 44
REFOCON
(3)
ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 0-00 0000 62, 45
CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 62, 345
CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 62, 345
RCON IPEN
—CMRI TO PD POR BOR 0-11 1100 60, 62,
135
TMR1H
(2)
/ Timer1 Register High Byte xxxx xxxx 62, 196
ODCON1
(3)
— — — CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD ---0 0000 62, 139
TMR1L
(2)
/ Timer1 Register Low Byte xxxx xxxx 62, 196
ODCON2
(3)
— — — — — — U2OD U1OD ---- --00 62, 139
T1CON
(2)
/ RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 62, 196
ODCON3
(3)
— — — — — — SPI2OD SPI1OD ---- --00 62, 139
TMR2
(2)
/ Timer2 Register 0000 0000 62, 201
PADCFG1
(3)
— — — — — — —PMPTTL---- ---0 62, 140
PR2
(2)
/ Timer2 Period Register 1111 1111 62, 201
MEMCON
(3)
EDBIS —WAIT1WAIT0— —WM1WMO0-00 --00 62, 108
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 62, 201
SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 62, 243,
278
SSP1ADD/ MSSP1 Address Register (I
2
C™ Slave mode), MSSP1 Baud Rate Reload Register (I
2
C™ Master mode) 0000 0000 62, 248
SSP1MSK
(5)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 62, 250
SSP1STAT SMP CKE D/A
PSR/WUA BF 0000 0000 62, 233,
244
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 62, 233,
245
SSP1CON2
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 62, 233,
246
GCEN
ACKSTAT ADMSK5
(6)
ADMSK4
(6)
ADMSK3
(6)
ADMSK2
(6)
ADMSK1
(6)
SEN
ADRESH A/D Result Register High Byte xxxx xxxx 63, 310
ADRESL A/D Result Register Low Byte xxxx xxxx 63, 310
ADCON0
(2)
/ VCFG1 VCFG0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 63, 301
ANCON1
(3)
PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 — — 0000 00-- 63, 301
ADCON1
(2)
/ ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0000 0000 63, 301
ANCON0
(3)
PCFG7 — — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0--0 0000 63, 301
WDTCON REGSLP LVDSTAT
—ADSHR— — —SWDTEN0x-0 ---0 63, 358
TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared-access SFRs.
Note 1: Bit 21 of the PC is only available in Serial Programming modes.
2: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
4: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
5: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
6: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 19.4.3.2 “Address
Masking Modes” for details
7: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
8: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.