Datasheet

PIC18F87J50 FAMILY
DS39775C-page 82 © 2009 Microchip Technology Inc.
5.3.5.1 Shared Address SFRs
In several locations in the SFR bank, a single address
is used to access two different hardware registers. In
these cases, a “legacy” register of the standard PIC18
SFR set (such as OSCCON, T1CON, etc.) shares its
address with an alternate register. These alternate reg-
isters are associated with enhanced configuration
options for peripherals, or with new device features not
included in the standard PIC18 SFR map. A complete
list of shared register addresses and the registers
associated with them is provided in Table 5-4.
Access to the alternate registers is enabled in software
by setting the ADSHR bit in the WDTCON register
(Register 5-3). ADSHR must be manually set or
cleared to access the alternate or legacy registers, as
required. Since the bit remains in a given state until
changed, users should always verify the state of
ADSHR before writing to any of the shared SFR
addresses.
5.3.5.2 Context Defined SFRs
In addition to the shared address SFRs, there are sev-
eral registers that share the same address in the SFR
space, but are not accessed with the ADSHR bit.
Instead, the register’s definition and use depends on
the operating mode of its associated peripheral. These
registers are:
• SSPxADD and SSPxMSK: These are two sepa-
rate hardware registers, accessed through a
single SFR address. The operating mode of the
MSSP modules determines which register is
being accessed. See Section 19.4.3.4 “7-Bit
Address Masking Mode” for additional details.
• PMADDRH/L and PMDOUT2H/L: In this case,
these named buffer pairs are actually the same
physical registers. The PMP module’s operating
mode determines what function the registers take
on. See Section 11.1.2 “Data Registers” for
additional details.
TABLE 5-4: SHARED SFR ADDRESSES FOR PIC18F87J50 FAMILY DEVICES
Address Name Address Name Address Name
FD3h (D) OSCCON
FCDh (D) T1CON FC2h (D) ADCON0
(A) REFOCON (A) ODCON3 (A) ANCON1
FCFh (D) TMR1H
FCCh (D) TMR2 FC1h (D) ADCON1
(A) ODCON1 (A) PADCFG1 (A) ANCON0
FCEh (D) TMR1L
FCBh (D) PR2 F77h (D) PR4
(A) ODCON2 (A) MEMCON
(1)
(A) CVRCON
Legend: (D) = Default SFR, accessible only when ADSHR = 0; (A) = Alternate SFR, accessible only when ADSHR = 1.
Note 1: Implemented in 80-pin devices only.
REGISTER 5-3: WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0 R-x U-0 R/W-0 U-0 U-0 U-0 U-0
REGSLP LVDSTAT
— ADSHR — — —SWDTEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 REGSLP: Voltage Regulator Low-Power Operation Enable bit
For details of bit operation, see Register 25-9 on page 359.
bit 6 LVDSTAT: Low-Voltage Detect Status bit
1 = V
DDCORE > 2.45V nominal
0 = V
DDCORE < 2.45V nominal
bit 5 Unimplemented: Read as ‘0’
bit 4 ADSHR: Shared Address SFR Select bit
1 = Alternate SFR is selected
0 = Default (legacy) SFR is selected
bit 3-1 Unimplemented: Read as ‘0’
bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit
For details of bit operation, see Register 25-9.