Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 65
PIC18F87J50 FAMILY
PORTJ Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
PORTH
Feature1 PIC18F8XJ5X 0000 xxxx uuuu uuuu uuuu uuuu
PORTG Feature1 PIC18F8XJ5X 000x xxxx 000u uuuu uuuu uuuu
PORTF Feature1 PIC18F8XJ5X x00x x0-- u00u u0-- u00u u0--
PORTE Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
PORTD Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
PORTC Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
PORTB Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
PORTA Feature1 PIC18F8XJ5X --0x 0000 --0u 0000 --uu uuuu
SPBRGH1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
BAUDCON1 Feature1 PIC18F8XJ5X 0100 0-00 0100 0-00 uuuu u-uu
SPBRGH2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
BAUDCON2 Feature1 PIC18F8XJ5X 0100 0-00 0100 0-00 uuuu u-uu
TMR3H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
T3CON Feature1 PIC18F8XJ5X 0000 0000 uuuu uuuu uuuu uuuu
TMR4 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
PR4 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 1111 1111
CVRCON Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
T4CON Feature1 PIC18F8XJ5X -000 0000 -000 0000 -uuu uuuu
CCPR4H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
CCPR4L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
CCP4CON Feature1 PIC18F8XJ5X --00 0000 --00 0000 --uu uuuu
CCPR5H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
CCPR5L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
CCP5CON Feature1 PIC18F8XJ5X --00 0000 --00 0000 --uu uuuu
SSP2BUF Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
SSP2ADD Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
SSP2MSK Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
SSP2STAT Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu
SSP2CON1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
SSP2CON2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
CMSTAT Feature1 PIC18F8XJ5X ---- --11 ---- --11 ---- --uu
TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.