Datasheet

PIC18F87J50 FAMILY
DS39775C-page 64 © 2009 Microchip Technology Inc.
IPR3 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu
PIR3 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
(3)
PIE3 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
IPR2 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu
PIR2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
(3)
PIE2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
IPR1 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu
PIR1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
(3)
PIE1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
RCSTA2 Feature1 PIC18F8XJ5X 0000 000x 0000 000x uuuu uuuu
OSCTUNE Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
TRISJ
Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu
TRISH Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu
TRISG Feature1 PIC18F8XJ5X ---1 1111 ---1 1111 ---u uuuu
TRISF Feature1 PIC18F8XJ5X 111- -1-- 111- -1-- uuu- -u--
TRISE Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu
TRISD Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu
TRISC Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu
TRISB Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu
TRISA Feature1 PIC18F8XJ5X --11 1111 --11 1111 --uu uuuu
LATJ
Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
LATH Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
LATG Feature1 PIC18F8XJ5X ---x xxxx ---u uuuu ---u uuuu
LATF Feature1 PIC18F8XJ5X xxxx xx-- uuuu uu-- uuuu uu--
LATE Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
LATD Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
LATC Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
LATB Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
LATA Feature1 PIC18F8XJ5X --xx xxxx --uu uuuu --uu uuuu
TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.