Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 63
PIC18F87J50 FAMILY
ADRESH Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
ADCON1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
ANCON0 Feature1 PIC18F8XJ5X 0--0 0000 u--u uuuu u--u uuuu
ANCON1 Feature1 PIC18F8XJ5X 0000 00-- uuuu uu-- uuuu uu--
WDTCON Feature1 PIC18F8XJ5X 0x-0 ---0 0x-u ---0 ux-u ---u
ECCP1AS Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
ECCP1DEL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
CCPR1H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
ECCP2AS Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
ECCP2DEL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
CCPR2H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
ECCP3AS Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
ECCP3DEL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
CCPR3H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
CCPR3L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
CCP3CON Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
SPBRG1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
RCREG1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
TXREG1 Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA1 Feature1 PIC18F8XJ5X 0000 0010 0000 0010 uuuu uuuu
RCSTA1 Feature1 PIC18F8XJ5X 0000 000x 0000 000x uuuu uuuu
SPBRG2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
RCREG2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
TXREG2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
TXSTA2 Feature1 PIC18F8XJ5X 0000 0010 0000 0010 uuuu uuuu
EECON2 Feature1 PIC18F8XJ5X ---- ---- ---- ---- ---- ----
EECON1 Feature1 PIC18F8XJ5X --00 x00- --00 u00- --00 u00-
TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.