Datasheet

PIC18F87J50 FAMILY
DS39775C-page 62 © 2009 Microchip Technology Inc.
INDF2 Feature1 PIC18F8XJ5X N/A N/A N/A
POSTINC2 Feature1 PIC18F8XJ5X N/A N/A N/A
POSTDEC2 Feature1 PIC18F8XJ5X N/A N/A N/A
PREINC2 Feature1 PIC18F8XJ5X N/A N/A N/A
PLUSW2 Feature1 PIC18F8XJ5X N/A N/A N/A
FSR2H Feature1 PIC18F8XJ5X ---- xxxx ---- uuuu ---- uuuu
FSR2L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
STATUS Feature1 PIC18F8XJ5X ---x xxxx ---u uuuu ---u uuuu
TMR0H Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
TMR0L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
T0CON Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu
OSCCON Feature1 PIC18F8XJ5X 0110 q100 0110 q100 0110 q10u
REFOCON Feature1 PIC18F8XJ5X 0-00 0000 u-uu uuuu u-uu uuuu
CM1CON Feature1 PIC18F8XJ5X 0001 1111 uuuu uuuu uuuu uuuu
CM2CON Feature1 PIC18F8XJ5X 0001 1111 uuuu uuuu uuuu uuuu
RCON
(4)
Feature1 PIC18F8XJ5X 0-11 1100 0-qq qquu u-qq qquu
TMR1H Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
ODCON1 Feature1 PIC18F8XJ5X ---0 0000 ---u uuuu ---u uuuu
TMR1L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
ODCON2 Feature1 PIC18F8XJ5X ---- --00 ---- --uu ---- --uu
T1CON Feature1 PIC18F8XJ5X 0000 0000 u0uu uuuu uuuu uuuu
ODCON3 Feature1 PIC18F8XJ5X ---- --00 ---- --uu ---- --uu
TMR2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
PADCFG1 Feature1 PIC18F8XJ5X ---- ---0 ---- ---u ---- ---u
PR2 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 1111 1111
MEMCON
Feature1 PIC18F8XJ5X 0-00 --00 0-00 --00 u-uu --uu
T2CON Feature1 PIC18F8XJ5X -000 0000 -000 0000 -uuu uuuu
SSP1BUF Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
SSP1ADD Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
SSP1MSK Feature1 PIC18F8XJ5X 1111 1111 uuuu uuuu uuuu uuuu
SSP1STAT Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
SSP1CON1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
SSP1CON2 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.