Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 61
PIC18F87J50 FAMILY
TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
TOSU Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---0 uuuu
(1)
TOSH Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
(1)
TOSL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
(1)
STKPTR Feature1 PIC18F8XJ5X 00-0 0000 uu-0 0000 uu-u uuuu
(1)
PCLATU Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---u uuuu
PCLATH Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
PCL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 PC + 2
(2)
TBLPTRU Feature1 PIC18F8XJ5X --00 0000 --00 0000 --uu uuuu
TBLPTRH Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
TBLPTRL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
TABLAT Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu
PRODH Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
PRODL Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
INTCON Feature1 PIC18F8XJ5X 0000 000x 0000 000u uuuu uuuu
(3)
INTCON2 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu
(3)
INTCON3 Feature1 PIC18F8XJ5X 1100 0000 1100 0000 uuuu uuuu
(3)
INDF0 Feature1 PIC18F8XJ5X N/A N/A N/A
POSTINC0 Feature1 PIC18F8XJ5X N/A N/A N/A
POSTDEC0 Feature1 PIC18F8XJ5X N/A N/A N/A
PREINC0 Feature1 PIC18F8XJ5X N/A N/A N/A
PLUSW0 Feature1 PIC18F8XJ5X N/A N/A N/A
FSR0H Feature1 PIC18F8XJ5X ---- xxxx ---- uuuu ---- uuuu
FSR0L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
WREG Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 Feature1 PIC18F8XJ5X N/A N/A N/A
POSTINC1 Feature1 PIC18F8XJ5X N/A N/A N/A
POSTDEC1 Feature1 PIC18F8XJ5X N/A N/A N/A
PREINC1 Feature1 PIC18F8XJ5X N/A N/A N/A
PLUSW1 Feature1 PIC18F8XJ5X N/A N/A N/A
FSR1H Feature1 PIC18F8XJ5X ---- xxxx ---- uuuu ---- uuuu
FSR1L Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu
BSR Feature1 PIC18F8XJ5X ---- 0000 ---- 0000 ---- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.