Datasheet

PIC18F87J50 FAMILY
DS39775C-page 58 © 2009 Microchip Technology Inc.
A CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event
Resets. As with all hard and power Reset events, the
device Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
4.6 Power-up Timer (PWRT)
PIC18F87J10 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F87J10 fam-
ily devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32 μs = 66 ms. While the PWRT
is counting, the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
4.6.1 TIME-OUT SEQUENCE
The PWRT time-out is invoked after the POR pulse has
cleared. The total time-out will vary based on the status
of the PWRT. Figure 4-3, Figure 4-4, Figure 4-5 and
Figure 4-6 all depict time-out sequences on power-up
with the Power-up Timer.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR
high will begin execution immediately if a clock
source is available (Figure 4-5). This is useful for
testing purposes, or to synchronize more than one
PIC18FXXXX device operating in parallel.
FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR
NOT TIED TO VDD): CASE 1
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET