Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 57
PIC18F87J50 FAMILY
4.2 Master Clear (MCLR)
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR
Reset path
which detects and ignores small pulses.
The MCLR
pin is not driven low by any internal Resets,
including the WDT.
4.3 Power-on Reset (POR)
A Power-on Reset condition is generated on-chip
whenever V
DD rises above a certain threshold. This
allows the device to start in the initialized state when
V
DD is adequate for operation.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
V
DD is specified (parameter D004). For a slow rise
time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR
bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR
is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any Power-on Reset.
4.4 Brown-out Reset (BOR)
The PIC18F87J10 family of devices incorporates a
simple BOR function when the internal regulator is
enabled (ENVREG pin is tied to V
DD). Any drop of VDD
below VBOR (parameter D005) for greater than time
T
BOR (parameter 35) will reset the device. A Reset may
or may not occur if V
DD falls below VBOR for less than
T
BOR. The chip will remain in Brown-out Reset until
V
DD rises above VBOR.
Once a BOR has occurred, the Power-up Timer will
keep the chip in Reset for T
PWRT (parameter 33). If
V
DD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be initialized. Once V
DD
rises above VBOR, the Power-up Timer will execute the
additional time delay.
FIGURE 4-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD POWER-U P)
4.4.1 DETECTING BOR
The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR
alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR
is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
If the voltage regulator is disabled, Brown-out Reset
functionality is disabled. In this case, the BOR
bit
cannot be used to determine a Brown-out Reset event.
The BOR
bit is still cleared by a Power-on Reset event.
4.5 Configuration Mismatch (CM)
The Configuration Mismatch (CM) Reset is designed to
detect and attempt to recover from random, memory
corrupting events. These include Electrostatic
Discharge (ESD) events, which can cause widespread
single-bit changes throughout the device, and result in
catastrophic failure.
In PIC18FXXJ Flash devices, the device Configuration
registers (located in the configuration memory space)
are continuously monitored during operation by com-
paring their values to complimentary shadow registers.
If a mismatch is detected between the two sets of
registers, a CM Reset automatically occurs. These
events are captured by the CM
bit (RCON<5>). The
state of the bit is set to ‘0’ whenever a CM event occurs;
it does not change for any other Reset event.
Note 1: External Power-on Reset circuit is required
only if the V
DD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when V
DD powers down.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR
from external capacitor C, in the event
of MCLR
/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
R
D
V
DD
MCLR
PIC18F87J50
VDD