Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 473
PIC18F87J50 FAMILY
SUBFWB .......................................................................... 400
SUBLW ............................................................................ 401
SUBULNK ........................................................................ 411
SUBWF ............................................................................ 401
SUBWFB .......................................................................... 402
SWAPF ............................................................................ 402
T
Table Pointer Operations (table) ...................................... 100
Table Reads/Table Writes ................................................. 75
TBLRD ............................................................................. 403
TBLWT ............................................................................. 404
Timer0 .............................................................................. 191
Associated Registers ............................................... 193
Operation ................................................................. 192
Overflow Interrupt .................................................... 193
Prescaler .................................................................. 193
Switching Assignment ...................................... 193
Prescaler Assignment (PSA Bit) .............................. 193
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 193
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 192
Source Edge Select (T0SE Bit) ................................ 192
Source Select (T0CS Bit) ......................................... 192
Timer1 .............................................................................. 195
16-Bit Read/Write Mode ........................................... 197
Associated Registers ............................................... 200
Interrupt .................................................................... 198
Operation ................................................................. 196
Oscillator .......................................................... 195, 197
Layout Considerations ..................................... 197
Overflow Interrupt .................................................... 195
Resetting, Using the ECCP Special Event Trigger .. 198
Special Event Trigger (ECCP) ................................. 220
TMR1H Register ...................................................... 195
TMR1L Register ....................................................... 195
Use as a Clock Source ............................................ 197
Use as a Real-Time Clock ....................................... 198
Timer2 .............................................................................. 201
Associated Registers ............................................... 202
Interrupt .................................................................... 202
Operation ................................................................. 201
Output ...................................................................... 202
PR2 Register ............................................................ 221
TMR2 to PR2 Match Interrupt .................................. 221
Timer3 .............................................................................. 203
16-Bit Read/Write Mode ........................................... 205
Associated Registers ............................................... 205
Operation ................................................................. 204
Oscillator .......................................................... 203, 205
Overflow Interrupt ............................................ 203, 205
Special Event Trigger (ECCP) ................................. 205
TMR3H Register ...................................................... 203
TMR3L Register ....................................................... 203
Timer4 .............................................................................. 207
Associated Registers ............................................... 208
MSSP Clock Shift ..................................................... 208
Operation ................................................................. 207
Postscaler. See Postscaler, Timer4.
PR4 Register ............................................................ 207
Prescaler. See Prescaler, Timer4.
TMR4 Register ......................................................... 207
TMR4 to PR4 Match Interrupt .......................... 207, 208
Timing Diagrams
A/D Conversion ........................................................ 456
Asynchronous Reception ......................................... 292
Asynchronous Transmission ................................... 290
Asynchronous Transmission (Back-to-Back) ........... 290
Automatic Baud Rate Calculation ............................ 288
Auto-Wake-up Bit (WUE) During Normal Operation 293
Auto-Wake-up Bit (WUE) During Sleep ................... 293
Baud Rate Generator with Clock Arbitration ............ 266
BRG Overflow Sequence ........................................ 288
BRG Reset Due to SDAx Arbitration During Start Condi-
tion ................................................................... 275
Bus Collision During a Repeated Start Condition (Case
1) ..................................................................... 276
Bus Collision During a Repeated Start Condition (Case
2) ..................................................................... 276
Bus Collision During a Start Condition (SCLx = 0) .. 275
Bus Collision During a Stop Condition (Case 1) ...... 277
Bus Collision During a Stop Condition (Case 2) ...... 277
Bus Collision During Start Condition (SDAx Only) .. 274
Bus Collision for Transmit and Acknowledge .......... 273
Capture/Compare/PWM (Including ECCP Modules) 444
CLKO and I/O .......................................................... 439
Clock Synchronization ............................................. 259
Clock/Instruction Cycle .............................................. 76
EUSARTx Synchronous Receive (Master/Slave) .... 455
EUSARTx Synchronous Transmission (Master/Slave) .
455
Example SPI Master Mode (CKE = 0) ..................... 447
Example SPI Master Mode (CKE = 1) ..................... 448
Example SPI Slave Mode (CKE = 0) ....................... 449
Example SPI Slave Mode (CKE = 1) ....................... 450
External Clock ......................................................... 437
External Memory Bus for SLEEP (Extended Microcon-
troller Mode) ............................................ 114, 116
External Memory Bus for TBLRD (Extended Microcon-
troller Mode) ............................................ 114, 116
Fail-Safe Clock Monitor ........................................... 363
First Start Bit Timing ................................................ 267
Full-Bridge PWM Output .......................................... 225
Half-Bridge PWM Output ......................................... 224
I
2
C Acknowledge Sequence .................................... 272
I
2
C Bus Data ............................................................ 451
I
2
C Bus Start/Stop Bits ............................................ 451
I
2
C Master Mode (7 or 10-Bit Transmission) ........... 270
I
2
C Master Mode (7-Bit Reception) ......................... 271
I
2
C Slave Mode (10-Bit Reception, SEN = 0, ADMSK =
01001) ............................................................. 255
I
2
C Slave Mode (10-Bit Reception, SEN = 0) .......... 256
I
2
C Slave Mode (10-Bit Reception, SEN = 1) .......... 261
I
2
C Slave Mode (10-Bit Transmission) .................... 257
I
2
C Slave Mode (7-Bit Reception, SEN = 0, ADMSK =
01011) ............................................................. 253
I
2
C Slave Mode (7-Bit Reception, SEN = 0) ............ 252
I
2
C Slave Mode (7-Bit Reception, SEN = 1) ............ 260
I
2
C Slave Mode (7-Bit Transmission) ...................... 254
I
2
C Slave Mode General Call Address Sequence (7 or
10-Bit Address Mode) ...................................... 262
I
2
C Stop Condition Receive or Transmit Mode ........ 272
MSSPx I
2
C Bus Data ............................................... 453
MSSPx I
2
C Bus Start/Stop Bits ............................... 453
Parallel Master Port Read ....................................... 445
Parallel Master Port Write ........................................ 446
Parallel Slave Port Read ................................. 176, 179
Parallel Slave Port Write .................................. 176, 179
Program Memory Read ........................................... 440
Program Memory Write ........................................... 441
PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Dis-